Overcurrent protective device

ABSTRACT

An overcurrent protective device of the time delay type is provided which is responsive to the current in an electrical circuit which is being protected. The protective device includes means for producing periodic output pulses of current each having substantially a predetermined width or duration, the frequency and magnitude of said pulses both varying with the current to which the device is responsive. When the current in the associated circuit increases to a predetermined level or value, the pulses are applied to a timing or integrating capacitor to provide an output voltage which varies in a substantially linear manner with the square of the current to which the protective device is responsive.

United States atent Watson et al.

[451 May 30, 1972 [54] OVERCURRENT PROTECTIVE DEVICE WestinghouseElectric Corporation, Pittsburgh, Pa.

22 Filed: June 18,1970

21 Appl.No.: 47,625

[73] Assignee:

Related US. Application Data [63] Continuation of Ser. No. 765,584, Oct.7, I968.

[52] U.S.Cl ..3l7/36 TD,317/33 SC, 317/38, 317/49, 3l7/l41 S [51] Int.Cl. v ..H01h 47/18 R25,762 4/1965 Kotheimer ..3l7/36 TD 3,419,75712/1968 Steen ..317/36 TD 3,444,434 5/1969 Zocholl ...3 1 7/36 TD3,484,652 12/1969 Thiele ..3 l7/49 X Primary Examiner-James D. TrammellAttorneyA. T. Stratton and Clement L. McHale [57] ABSTRACT Anovercurrent protective device of the time delay type is provided whichis responsive to the current in an electrical circuit which is beingprotected. The protective device includes means for producing periodicoutput pulses of current each having substantially a predetermined widthor duration, the frequency and magnitude of said pulses both varyingwith the current to which the device is responsive. When the current inthe associated circuit increases to a predetermined level or value, thepulses are applied to a timing or integrating capacitor to provide anoutput voltage which varies in a substantially linear manner with thesquare of the current to which the protective device is responsive.

9 Claims, 6 Drawing Figures Patented May 30, 1972 4 Sheets-Sheet 1 himEwmmno 028% 0 E 09 I mm w L INVENTORS John D. Wotsonfroncis T. Thompsonand Frederick 0. Johnson.

R E 6 M 2 P5050 @2525 :REG Sn? 5&3 E28 F I G 3.

ATTORNEY Patented May 30, 1972 4 Sheets-Sheet 2 OON NQN mmm [I NNN W3\w? I Patented May 30, 1972 4 Sheets-Sheet 3 IOO % OF RATED CURRENTOVERCURRENT PROTECTIVE DEVICE This is a continuation of application Ser.No. 765,584, filed Oct. 7, 1968.

CROSS-REFERENCES TO RELATED APPLICATIONS Certain inventions disclosed inthe present application are disclosed and claimed in copendingapplication Ser. No. 765,582 filed Oct. 7, 1968 by .I. D. Watson, acontinuation of which was filed on June 18, 1970 as copendingapplication Ser. No. 47,624 and which issued June 29, 1971 as US. Pat.No. 3,590,326 and copending application Ser. No. 765,552 filed Oct. 7,1968 by W. H. South and J. H. Taylor (which issued Nov. 24, 1970 as US.Pat. No. 3,543,094).

BACKGROUND OF THE INVENTION This invention relates to overcurrentprotective devices and more particularly to such devices of the timedelay type.

In the past, overcurrent protective relay devices having an inversetime-overcurrent operating characteristic have been primarily of theelectromechanical type. More recently, various types of staticovercurrent protective relay devices having inverse time-overcurrentoperating characteristics have been proposed. One static protectiverelay device of the type described employs periodic pulses of current offixed duration whose magnitude and frequency both vary with the currentin the circuit being protected and which are applies to charge a timingcapacitor with the voltage across the capacitor reaching a predeterminedvalue after a time period which varies inversely approximately with thesquare of the overcurrent. For greater accuracy in such a protectiverelay device, it is desirable that the operating characteristic of such.a device be such as to provide an output after a time delay which moreprecisely varies inversely with the square of the overcurrent in thecircuit being protected.

SUMMARY OF THE INVENTION In accordance with the invention, an inversetime-overcurrent protective relay device is provided in which periodicpulses of current are produced each having substantially a predeterminedwidth or duration with both the frequency and the magnitude of thepulses varying in a substantially linear manner with the overcurrent inthe circuit being protected. In order that the magnitude of the pulsesvary in the desired manner, the protective device includes means forobtaining a unidirectional voltage which is directly proportional to theovercurrent in the circuit being protected and means for converting theunidirectional voltage to substantially a predetermined unidirectionalcurrent having a magnitude or value which varies in a substantiallylinear manner with the unidirectional voltage. The pulses of current arethen applied to a timing capacitor which is normally prevented fromaccumulating a charge in response to the pulses of current by a controlmeans until the overcurrent increases to a predetermined level or value.After the overcurrent increases to the predetermined value and persistsfor a time period which varies substantially inversely with the squareof the overcurrent in the circuit being protected, the charge on thetiming capacitor as well as the corresponding voltage across thecapacitor increases to a predetermined or threshold level to initiate orprovide an output from the protective relay device. In one aspect of theapplicants invention, the protective device may be responsive only tothe highest of a plurality of overcurrents in a polyphase electricalcircuit.

It is therefore an object of this invention to provide an overcurrentprotective relay device having a time delay which more precisely variesinversely with the square of the overcurrent in thecircuit beingprotected.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects of the invention will beapparent from the following detailed description taken in conjunctionwith the accompanying drawings in which:

FIG. 1 is a schematic diagram, partly in block form, of an overcurrentprotective relay device of the time delay type embodying the inventionand associated with an electrical system or circuit;

FIG. 2 is a detailed schematic diagram of a portion of the protectivedevice which is shown in block form in FIG. 1;

FIG. 3 is a detailed schematic diagram of an optional portion of theprotective device which is shown in block form in FIG. 1;

FIG. 4 is a simplified or idealized graphical representationillustrating the operational characteristics of the protective deviceshown in FIG. 1;

FIG. 5 is a set of waveforms or graphs illustrating the operation of aportion of the protective device shown in FIG. I; and

FIG. 6 is a graphical representation of the voltage-ampere of theprotective device shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawingsand FIG. 1 in particular, there is illustrated an overcurrent protectiverelay device associated with the line conductors L1, L2 and L3 of anelectrical power system or circuit to be protected. The electricalsystem may be of any desired type such as a single-phase system or apolyphase system. It will be assumed for purposes of the presentdescription that the electrical system is a threephase alternatingcurrent system represented by the line conductors L1, L2 and L3 anddesigned for operation at a frequency of 60 cycles per second.

A circuit breaker CB is provided for segregating or isolating portionsof the electrical system under certain abnormal or fault conditions,such as an overcurrent condition. The circuit breaker CB includes aplurality of separable line contacts BCl, BC2 and BC3 which are closedwhen the circuit breaker isclosed and which are opened when the circuitbreaker is opened. The circuit breaker CB also includes a trip coil 36which when energized while the circuit breaker is closed results in atripping or opening operation of the circuit breaker CB. As illustrateddiagrammatically in FIG. 1, energization of the trip coil 36 may actuatean operating member 32 to release a latch member 38 to thereby actuatean opening operation of the line contacts BCl, BC2 and BC3 under theinfluence of a suitable operating means, such as the spring 34, whichmay be operatively connected to said line contacts.

In general, the protective device shown in FIG. I is arranged to respondto the highest of the line currents which flow in the conductors L1, L2and L3 to energize the trip coil 36 and to actuate the tripping of thecircuit breaker CB after a time delay which is initiated when thehighest of the line currents in the conductors L1, L2 and L3 exceeds apredetermined value and which varies substantially inversely with thesquare of the highest of the line currents in said conductors for apredetermined range of overcurrents in said conductors. Where desired,the protective device shown in FIG. I may also respond to the highest ofthe line currents in the line conductors L1, L2 and L3 to energize thetrip coil 36 and to actuate the tripping of the circuit breaker CB in asubstantially instantaneous manner without any intentional time delaywhen the highest of the line currents in said conductors exceeds apredetermined value or to energize the trip coil 36 and to actuate thetripping of the circuit breaker CB after a substantially fixed orpredetennined time delay when the highest of the line currents in saidconductors exceeds a predetermined value. In addition, where required,the protective device shown in FIG. 1 may respond to a predeterminedground current in the electrical system which includes the lineconductors L1, L2 and L3 to energize the trip coil 36 and to actuate thetripping of the circuit breaker CB after a substantially fixed orpredetermined time delay when the ground current exceeds a predeterminedvalue which initiates the start of the substantially fixed orpredetermined time delay.

tors L1, L2 and L3, a plurality of current transformers or sensors CTl,CT2 and GT3 are provided as shown in FIG. 1 with the primary windings ofsaid current transformers being energized in accordance with the linecurrents in the line conductors L1, L2 and L3 respectively. Thesecondary windings of the current transformers CTl, CT2, CT3 are wyeconnected between the neutral terminal or conductor NTl and therespective output terminals 52, 62, and 72. In order to further stepdown the output currents of the current transformer CT 1 CT2, and GT3,the intermediate transformers T1, T2 and T3 which may be of thesaturating type are connected between the secondary windings of saidcurrent transformers and the input terminals of the power supply inputcircuit 100 of the protective device shown in FIG. 1. More specifically,the primary windings of the transformers T1, T2 and T3 are wye connectedbetween the output terminals 52, 62 and 72 respectively of the currenttransformers CTl, CT2 and CT3 respectively and the neutral terminal NT2with the neutral terminal NT2 being connected to the neutral terminalNTl of said current transformers through the primary winding of a groundcurrent transformer T4 where ground current tripping protection isdesired. Where ground current tripping protection is not required, theneutral terminal NT2 at the terminal 44 of the primary winding of theground current transformer T4 may be directly connected to the neutralterminal NTl of the current transformers CTl, CT2, and GT3. Thesecondary windings of the intermediate transformers T1, T2 and T3 areconnected to the input terminals 112 and 114, 122 and 124, and 132 and134, respectively, of the power supply input circuit 100 of theprotective device shown in FIG. 1 to provide three output currentswhich, in turn, are directly proportional to the line currents in theline conductors L1, L2 and L3 of the electrical system, as illustrated.

In order to rectify the alternating current outputs of the transformersT1, T2 and T3, the power supply input circuit 100 of the protectivedevice shown in FIG. 1 includes a plurality of full wave rectifiers 22,24, and 26, as illustrated in FIG. 2 ofthe drawings. As shown in FIG. 2,the input terminals of the full wave rectifier 22 are connected to theterminals 112 and 114 which, in turn, are connected across the secondarywinding of the transformer T1. Similarly, the input terminals of thefull wave rectifiers 24 and 26 at the terminals 122 and 124 and 132 and134, respectively, are connected across the secondary windings of thetransformers T2 and T3, respectively.

POWER SUPPLY INPUT CIRCUIT 100 In order to develop a plurality ofunidirectional voltages which correspond to and are directlyproportional to the line currents in the conductors L1, L2 and L3, thepower supply input circuit 100 of the protective device includes aplurality of resistors R1, R2, and R3 whose upper ends are connected tothe positive output terminals of the full wave rectifiers 22, 24 and 26respectively. The lower ends of the resistors R1, R2 and R3 areelectrically connected together at the conductor Pl. One or more filtercapacitors, as indicated at C13 in FIG. 2, is connected between theconductor P1 and the negative output terminals of the full waverectifiers 22, 24, 26 which are electrically connected together to acommon terminal, as indicated at the conductor N1. In order to providea'plurality of regulated, filtered unidirectional voltages for thebalance of the protective device shown in FIGS. 1 and 2, a seriescircuit is connected electrically in parallel with the capacitor C13between the conductor P1 and the common conductor N1 which includes theforward connected diode D23, a first reversely poled Zener diode Z1, asecond reversely poled Zener diode Z2 and a forward connected diode D25.

When the power supply input circuit 100 is initially energized from thecurrent transformers CTl, CT 2 and GT3 and the associated transformersT1, T2, T3, the three output currents from the full wave rectifiers 22,24 and 26 flow through the resistors R1, R2 and R3, respectively, todevelop three unidirectional voltages which are directly proportional tothe line currents in the conductors L1, L2 and L3, respectively and tocharge the capacitor C13. The voltage across the capacitor C13 increasesas the capacitor is charged from the full wave rectifiers 22, 24 and 26until the voltage across the capacitor C13 is sufiicient to cause theZener diodes Z1 and Z2 to break down and limit the voltage across thecapacitor C13 to substantially a predetermined value which is equal tothe total of the forward voltage drop across the diodes D23 and D25 andthe reverse breakdown voltages across the Zener diodes Z1 and 22. Theregulated and filtered voltage across the capacitor C13 which isavailable between the conductors P1 and N1 may, for example, be of theorder of 33 volts while the voltage available between the conductor P2and the common conductor N1 will be less than the voltage between theconductors P1 and N1 by the forward voltage drop across one or morediodes, as indicated by the diode D23 which represents one or morediodes connected in series. Similarly, the regulated voltage availablebetween the conductor P3 and the common conductor N1 will be less thanthe voltage between the conductors P1 and N1 by the forward voltage dropacross the diode D23 and the reverse breakdown voltage across the Zenerdiode Z1. It is to be noted that after the Zener diodes Z1 and Z2 breakdown during the initial charging of the capacitor C13, the threeunidirectional output cur rents from the full wave rectifiers 22, 24 and26 will flow from the positive terminals of said rectifiers through therespective resistors R1, R2 and R3 to the conductor P1 and then throughthe series circuit which includes the diode D23, the Zener diodes Z1 andZ2 and the diode 25 to the common conductor N1 which is connected to thenegative output terminals of the rectifiers 22, 24, 26. The diode 25represents one or more diodes connected in series as required in aparticular application.

In order to obtain a first unidirectional voltage which varies only withthe highest of the three unidirectional voltages across the resistorsR1, R2, R3 and, in turn, only with the highest of the line currents inthe conductors L1, L2 and L3, the power supply input circuit includes afirst auctioneering circuit which comprises the diodes D17, D18 and D19.The diodes D17, D18 and D19 are forward connected between the upper endsof the resistors R1, R2 and R3, respectively, at the positive outputterminals of the rectifiers 22, 24, and 26, respectively, and a commonvariable voltage output conductor or bus V1, as shown in FIG. 2. Theunidirectional output voltage of the first auctioneering circuit 110which is available or appears between the conductor V1 and the conductorPl will be equal to the'highest voltage across resistors R1, R2 and R3less the forward voltage drop across one of the diodes D17, D18 and D19since if the unidirectional voltage across one of said resistors exceedsthe unidirectional voltages across the other two of said resistors, twoof the three diodes D17, D18 and D19 will be blocked or reversed biasedby the highest unidirectional voltage which is present between theconductors V1 and P1. It is important to note that the unidirectionaloutput voltage which appears between the conductors V1 and P1 isunfiltered for reasons which will be explained hereinafter.

In order to obtain a second unidirectional output voltage which variesonly with the highest of the three unidirectional voltages across theresistors R1, R2 and R3 and in turn with only the highest of the linecurrents in the conductors L1, L2 and L3, the power supply input circuit100 includes a second auctioneering circuit which includes the diodesD20, D21 and D22. Similarly to the diodes of the first auctioneeringcircuit 110, the diodes D20, D21 and D22 are connected to the upper endsof the resistors R1, R2 and R3, respectively, at the positive outputterminals of the rectifiers 22, 24 and 26, respectively, and a commonvariable voltage output conductor V2 which forms part of the long timedelay tripping circuit 200, as shown in FIG. 2. The unidirectionaloutput voltage of the second auctioneering circuit 120 is availablebetween the conductors V2 and the conductor P1 and is equal to thehighest of the three unidirectional output voltages across the resistorsR1, R2 and R3 less the forward voltage drop across one of the diodesD20, D21 and D22. The unidirectional output voltage of the secondauctioneering circuit 120 is filtered by the capacitor C1 which isconnected between the conductor. V2 and the conductor P1. The secondauctioneering circuit 120 operates similarly to the first auctioneeringcircuit 110 in that when one of the three unidirectional voltages acrossthe resistors R1, R2, R3 exceeds the other two unidirectional voltages,two of the forward connected diodes D20, D21 and D22 will be blocked orreversed biased.

In order to prevent the operation of the protective device shown in FIG.1, prior to the time that the capacitor C13,

which may include one or more energy storing capacitors in a particularapplication, is fully charged or in the event that the capacitor C13should not be fully charged during the operation of the protectivedevice shown in FIG. 1, the power supply input circuit 100 includes thecontrol means or circuit 150 which comprises the NPN transistors Ql andQ2, as shown in FIG. 2. In general, thecontrol means 150 of the powersupply input circuit 100 is provided to insure that the capacitor C13has acquired sufficient charge or stored energy to adequately energizethe trip'coil 36 of the circuit breaker CB when called upon to do soduring the operation of the pro,- tective device shown in FIG. 1, aswill be explained in greater detail hereinafter. More specifically, thecontrol means 150 of the power supply input circuit 100 includes avoltage dividing network which comprises the resistors R5 and R6connected in series with one another, the series circuit beingelectrically connected in parallel with the diode D25 between the anodeof the diode D25 and the common or negative conductor N1. When thecapacitor C13 is fully charged and the Zener diodes Z1 and Z2 breakdown, the diode D25 limits the voltage across the series circuit whichincludes the resistors R5 and R6 to the forward voltage drop of thediode D25. In order to apply a drive current to the base of thetransistor Q1 when the capacitorCl3 is fully or adequately charged, thebase of the transistor T1 is connected to the junction point .betweenthe resistors R5 and R6, while the emitter of the transistor O1 isconnected to the common conductor N1. The collector of the transistor Q1is connected to the conductor P1 through a collector load resistor R4and is also directly connected or coupled to the base of the transistorQ2. The emitter of the transistor Q2 is also directly connected to thecommon conductor NI, while the collector of the transistor Q2 isconnected to the collector of the transistorQ15 which forms part of theoutput circuit 400, as shown in FIG. 2, through a conductor 262 and adiode D48 which is a normally blocked or reversed biased, isolatingdiode, whose purpose will be explained in more detail hereinafter.

In the operation of the control means 150, prior to the time that thecharge on the capacitor C13 and the corresponding voltage thereacross issufiicient to break down the Zener diodes Z1 and Z2 in the reversedirection or. whenever the charge on the capacitor C13 and thecorresponding voltage thereacross is insufficient to break down saidZener diodes during the operation of the overall protective device shownin FIG. 1, the current flowing in the base-emiter circuit of thetransistor Q1 will be insufficient to-actuate the transistor Q1 to -asaturated condition and the transistor Q1 will therefore besubstantially nonconducting or cutofi. Whenever the transistor O1 issubstantially nonconducting or cutofi and a unidirectional outputvoltage is present at the conductor Pl, current will flow from theconductor P1 to the conductor N1 through the resistor R4 and thebase-emitter circuit of the transistor Q2 to actuate the transistor Q2to a saturated condition in which the voltage drop across thecollector-emitter circuit of thetransistor Q2 will be relativelynegligible and the voltage or potential at the conductor 262 will bevery close to the potential at the common conductor N1. Whenever thepotential at the conductor 262 is held at a value which is very close tothe potential at the common conductor N I, the diode D48 in the outputcircuit 400 of the protective device will be or adequately chargedsufficiently to break down the Zener diodes Z1 and Z2 or whenever thecharge on the capacitor C13 and the corresponding voltage thereacross issufiicient to break down said Zener diodes in the reverse direction,current will flow through the series circuit which includes the diodeD23, the Zener diodes Z1 and 22, the resistor R5, and the base-emitterof the transistor 01 which is sufficient to actuate the transistor O1 toa saturated condition in which the current flowing in thecollector-emitter circuit of the transistor O1 is limited only by thevalue of the resistor R4 which is connected in series with the collectorof the transistor Q1 and'the voltage between the conductor PI and theconductor N1. When the transistor 01 is actuated to a saturatedcondition as just described, the potential at the base of the transistor02 will change to a potentialwhich is very close to the potential at thecommon conductor N1 and the current flow in the baseemitter circuit ofthe transistor Q2 will be reduced to a value less than that necessary tomaintain the transistor Q2 in a saturated condition and the transistorQ2 will therefore be actuated to a substantially nonconducting or cutoffcondition. When the transistor Q2 is actuated to a substantiallynonconducting or cutofi' condition, the potential at the conductor 262with respect to the potential at the conductor N1 will be raisedsufiiciently to block or reverse bias the diode D48 and the outputcircuit 400 of the protected device shown in FIG. 1 will be permitted tooperate in normal fashion, since the capacitor C13 will be assured asufiicient charge and corresponding voltage thereacross to energizethetrip coil 36 of the circuit breaker CB when called upon to do so duringthe operation of the protective device as shown in FIG. 1. It is to benoted that the value of the resistor R6 which forms part of the controlmeans 150 may be selected so as to determine the minimum current in thebase-emitter circuit of the transistor Q1 which is necessary to actuatethe transistor Q1 from a substantially nonconducting or cutoff conditionto a saturated condition to decrease the sensitivity of the controlmeans 150, as desired,

in a particular application.

LONG TIME DELAY TRIPPING CIRCUIT 200 In general, the long time delaytripping circuit 200 is connected between the power supply input circuitand the output or level detecting circuit 400 of the protective deviceshown in FIG. 1 to respond to the highest of the unidirectional voltagesdeveloped across the resistors R1, R2 and R3 which appear at theconductors V1 and V2 to actuate the output circuit 400 to energize thetrip coil36 of the circuit breaker CB and trip said circuit breaker openwhenever the highest of the line currents flowing in the line conductorsL1, L2 and L3 ex ceeds a predetermined value after a time delay whichvaries substantially inversely with the square of the overcurrent over apredetermined range of overcurrent and which is initiated when thehighest of the line currents in said conductors exceeds thepredetermined or threshold value. More specifically, the long time delaytripping circuit 200 includes the first and second substantiallyconstant current sources or circuits 210 and 220 respectively, which areconnected to the variable voltage output conductor V2 of the secondauctioneering circuit for converting the highest of the unidirectionalvoltages across the resistors Rl, R2 and R3 to first and secondsubstantially predetermined unidirectional output currents which aremaintained at substantiallyconstant, values for a particular value ofthe highest unidirectional voltageacross said resistors independently ofchanges in the loads connected at the outputs of said current circuits.The unidirectional output currents of the current circuits 210 and 220which vary in a substantially linear manner or are directly proportionalto the highest of the unidirectional voltages across the resistors R1,R2 and R3 and, intum, vary in a substantially linear manner or aredirectly proportional to the highest of the line currents in theconductors L1, L2 and L3 are then applied to a pulse generating circuit230 for producing output pulses of unidirectional current whosefrequency or repetition rate and magnitude or amplitude both vary in asubstantially linear manner with the highest of the line currents in theconductors L1, L2 and L3, with each of said pulses havinga-substantially predetermined width or duration. The output pulses ofunidirectional current from the pulse generating circuit 230 are appliedto a timing capacitor or integrating capacitor C4 to cumulatively chargethe capacitor C4 when permitted to do so by a level detecting circuit260 which is connected to the variable voltage conductor V1 to permitthe charging of the capacitor C4 when the highest of the line currentsin the conductors L1, L2 and L3 increases to substantially apredetermined or threshold overcurrent value. When the pulse generatingcircuit 230 is permitted to charge the capacitor C4 cumulatively aspermitted by the operation of the level detecting circuit 260, thecharge across the capacitor C4 increases gradually to a predetermined orthreshold value after a time delay which varies substantially inverselywith the square of the highest line current in the conductors L1, L2'and L3to actuate the operation of the output circuit 400 of theprotective device shown in FIG. 1 to energize the trip coil 36 of thecircuit breaker CB. In order to periodically increase the effectivevoltage at the upper terminal of the capacitor C4 for reasons which willbe explained hereinafter, the long time delay tripping circuit 200 alsoincludes an auxiliary pulse generating circuit 240 which is-responsiveto the output pulses of the pulse generating circuit 230 to periodicallyincrease the voltage between the upper terminal of the timing orintegrating capacitor C4 and the common conductor N1.

More specifically, the first current circuit means 210 is connected tothe second auctioneering circuit 120 for converting the highestunidirectional voltage across the resistors R1, R2 and R3 to a firstunidirectional output current which is maintained at substantially apredetermined or constant value for a particular value of the highestunidirectional voltage across said resistors and which varies in asubstantially linear manner with the highest unidirectional voltageacross said resistors.

The first current circuit means 210 comprises a PNP transistor Q5 andthe resistor R9 which is connected electrically in series with theemitter of the transistor Q5 between the variable voltage conductor V2at the upper end of the capacitor C1 and the emitter of the transistorT5. The baseof the transistor Q5 is connected to the conductorPZ inorder that the input voltage of the first circuit means 210 between theconductors V2 and P2 include the forward voltage drop of the diode D23which may include one or more forward connected diodes in a particularapplication to thereby compensate theinput voltage of the first circuitmeans 210 for the forward voltage drop across one of the diodes D20, D21and D22 which is connected between one of the resistors R1, R2 and R3having the highest unidirectional voltage thereacross and the variableconductor V2 and the forward voltage drop across the baseemitter circuitof the transistor Q5. The emitter current of the transistor O5 istherefore equal to the ratio of the highest unidirectional voltageacross one of the resistors R1, R2 and R3 to the value of the resistorR9 which is connected in series with the emitter of the transistor Q5.The unidirectional output current of the first circuit means 210 isavailable at the collector of the transistor Q5 which is connected tothe left side of the capacitor C3 at the terminal 272. In order tomaintain the unidirectional output current of the first circuit means210 at substantially a predetermined or constant value for particularvalue of the highest unidirectional voltage across the resistors R1, R2and R3, the input voltage applied across the series circuit whichincludes the resistor R9 and the emitterbase circuit of the transistorQ5 should be relatively high, such as the order of 10 to 20 times theforward voltage drop across the emitter-base circuit of the transistorQ5. In addition, the transistor Q5 should have a relatively high currentgain or ratio of emitter current to base current, such as of the orderof 100, at the particular level of output current at which thetransistor 05 is operating in order that the base current of thepredetermined or constant value for a particular value of the highestunidirectional voltage across the resistors R1, R2 and R3 independent ofchanges in whatever load circuit is connected to the collector of thetransistor Q5 and the unidirectional output current at the collector ofthe transistor Q5 varies in a substantially linear manner with thehighest unidirectional voltage across the resistors R1, R2 and R3 and,in turn, with the highest line current in the conductors L1, L2 and L3.I

Similarly, the second current circuit means 220 is connected to thefirst auctioneering circuit 1 10 for converting the highestunidirectional voltage across the resistors R1, R2 and R3 to a secondunidirectional output current which is mainis connected to the output ofthe second current circuit means 220 and which varies in a substantiallylinear manner with the highest unidirectional voltage across saidresistors. The second current circuit means 220 comprises the PNPtransistor Q6, the resistor R13 which is connected in series with theemitter of the transistor 06 and the rheostat or variable resistancemeans R38 which is connected in series with the resistor R13 and theemitter of the transistor 216 between the second variable voltageconductor V2 and the emitter of the transistor Q6. The base of thetransistor Q6 is also connected to the conductor P2 in order that theinput voltage of the second circuit means 220 between the conductor V2and the conductor P2 include the forward voltage drop across the diodeD23 to thereby compensate the input voltage of the second circuit means220 for the forward voltage drop across one of the diodesD20, D21 andD22 which is connected between one of the resistors R1, R2 and R3 havingthe highest unidirectional voltage thereacross and the variable voltageconductor V2 and the forward voltage drop across the emitter-basecircuit of the transistor Q6. The emitter current of the transistor O6is substantially equal to the input voltage of the second circuit means220 between the conductors V2 and P2 divided by the total resistance ofthe rheostat R38 and the resistor R13. Since the transistor Q6 isselected to have a relatively high current gain or ratio of emittercurrent to base current, such as of the order of 100, at the particularlevel of the emitter current at which the transistor O6 is operating,the base current of the transistor 06 is substantially negligible andthe unidirectional output current of the transistor Q6 at the collectortransistor Q6 is substantially equal to the emitter current of thetransistor Q6. In order that the unidirectional output current of thesecond circuit means 220 at the collector of the transistor Q6 bemaintained at substantially a predetermined constant value forparticular value of the highest unidirectional voltage across theresistors R1, R2 and R3, the input voltage applied to the second circuitmeans 20 between the conductor V2 and the conductor P2 should berelatively large compared with the forward voltage drop in theemitter-base circuit of the transistor Q6. The setting of the rheostatR38 may be adjusted to vary the unidirectional output current of thesecond circuit means 220 at the collector of the transistor Q6 whichcorresponds to a particular value of the highest unidirectional voltageacross the resistors R1, R2

and R3 and, in turn, with the highest line current in the conductors L1,L2 and L3. It is to be noted that the portion of the linear manner withthe highest unidirectional voltage across the resistors R1, R2 and R3and, in turn, with the highest line current in the conductors L1, L2 andL3 respectively. The collector of the transistor Q6 of the secondcurrent circuit means 220 is connected to the upper side of the timingor integrating capacitor C4 through the diode D30 and cumulativelycharges the timing capacitor C4 when permitted to do so by the operationof other portions of the overall protective device shown in FIG. 1.

In order to control the application of the unidirectional output currentfrom the second current circuit means 220 to the timing capacitor C4 inthe form of periodic pulses of current whose frequency or repetitionrate and magnitude or amplitude both vary in a substantially linearmanner or are directly proportional to the highest line current in theconductors L1, L2 and L3 and whose width remains at a substantiallypredetermined or constant duration or time width when permitted to do soby the level detecting circuit 260 of the long time delay trippingcircuit 200, the pulse generating circuit 230 is connected to the firstand second current circuit means 210 and 220, respectively, and to theconductors P1 and P3 which supply regulated and filtered unidirectionalvoltages to said pulse generating circuit.

More specifically, the pulse generating circuit 230 comprises abreakover device, such as the unijunction transistor or double basediode Q4, the NPN transistor Q7 and the energy storing capacitor C3. Itis to be noted that the unidirectional, regulated potential at theconductor Pl may for example be approximately 33 volts which is positivewith respect to the potential at the common conductor N1 while theunidirectional, regulated potential at the conductor P3 may beapproximately one-half the voltage at the conductor P1 or may be, forexample, at a voltage of approximately 16.5 volts which is positive withrespect to the potential at the common conductor N]. The lower base ofthe unijunction transistor Q4 is connected directly to the commonconductor N1 While the upper base of the transistor T4 is connected tothe conductor P3 through the resistor R10 to apply a substantiallypredetermined interbase potential to the unijunction transistor Q4 priorto the breakover of the transistor Q4. The emitter of the unijunctiontransistor O4 is connected to the left-side of the capacitor C3 at theterminal 272 which, in turn, is connected to the first circuit means 210at the collector of the transistor Q5. The right side of the capacitorC3 at the terminal 282 is connected to the conductor Pl through theresistor R11 and to the base of the transistor 07 through the diode D28.The base of the transistor 07 is connected to the common conductor N1through the resistor R12 which acts as a shunt resistor electrically inparallel with the base-emitter circuit of the transistor 07 to decreasethe sensitivity of the transistor Q7 and to establish the minimumcurrent in the base emitter circuit of the transistor Q7 necessary toactuate the transistor O7 to a saturated or substantially conductingcondition. The emitter of the transistor O7 is directly connected to thecommon conductor N1, while the collector of the transistor O7 isconnected to the collector of the transistor Q6 which forms part of thesecond current circuit means 220 and is also connected to the upper sideof the timing or integrating capacitor C4 through the diode D30. It isto be noted that the resistor R10 which is connected between the upperbase of the unijunction transistor Q4 and the conductor P3 also assistsin temperature compensating the pulse generating circuit 230 for changesin the operating characteristics of unijunction transistor 24 whichresults from changes in the environmental temperature.

In general, the pulse generating circuit 230 operates as a relaxationoscillator or sawtooth voltage generator which depends upon theoperating characteristics of the break-over device which is employed aspart of the circuit and which is illustrated in the unijunctiontransistor Q4. Referring to FIG. 6,

the typical operating characteristics of a suitable breakover devicesuch as the unijunction transistor Q4, a four-layer diode, a transistorbreakover circuit or other suitable circuit is illustrated. Assumingthat a particular value of interbase potential is applied between theupper base and the lower base of the transistor ()4, the vertical axisin the graphical representation shown in FIG. 6 is the emitter voltagewith respect to the lower base while the horizontal axis represents theemitter current flow between the emitter and the lower base of thetransistor Q4. As shown in FIG. 6, when the voltage or potential appliedbetween the emitter and lower base of the transistor Q4 exceedssubstantially a predetermined fraction or percentage of the potentialapplied between the upper base and lower base of the transistor Q4, asindicated by the peak point voltage V the resistance or impedancebetween the emitter and the lower base of the transistor 04 willdecrease suddenly until the voltage between the emitter and the lowerbase of the transistor Q4 decreases to a lower valley voltage asindicated at V in FIG. 6. i

More specifically in considering the detailed operation of the pulsegenerating circuit 230, it will be assumed initially that the voltage orpotential applied between the emitter and the lower base of thetransistor O4 is less than the peak point voltage necessary to cause thetransistor Q4 to break over and that the transistor Q7 is being held ina substantially saturated condition by the base drive current whichflows from the positive conductor P1 through the resistor R11, theforward connected diode D28 and the base-emitter circuit of thetransistor O7 to the common or negative conductor N1. It is to be notedthat during the assumed initial operating conditions, the right side ofthe capacitor C3 at the terminal 282 will be held or clamped at apositive potential with respect to the common conductor N1 which isequal to the sum of the forward voltage drops across the diode D28 andthe base-emitter circuit of the transistor Q7. It is also to be notedthat the unidirectional output current of the second current circuitmeans 220 and the collector of the transistor Q6 which is maintained atsubstantially a predetermined value for a particular value of thehighest unidirectional voltage across the resistors R1, R2 and R3 willbe diverted away from or bypassed around the timing or integratingcapacitor C4 through the collector-emitter path of the transistor O7 tothe common or negative conductor N1 as longas the diode D28 is forwardbiased and the transistor 07 is held in a saturated condition.

In the operation of the pulse generating circuit 230, assuming that thehighest unidirectional voltage across the resistors R1, R2 and R3 whichis directly proportional to the highest line current flowing in theconductors L1, L2 and L3, the unidirectional output current from thefirst circuit means 210 which appears at the collector of the transistorQ5 will be maintained at a substantially predetermined or constant valueand will be applied to the left side of the energy storing capacitor C3at the terminal 272 to gradually charge the capacitor C3 in asubstantially linear manner until the voltage at the terminal 272exceeds the peak point voltage of the unijunction transistor Q4 and thetransistor Q4 breaks over and the voltage at the terminal 272 at theleft side of the capacitor C3 suddenly decreases from the peak pointvoltage V to the valley voltage V as indicated in FIG. 6 by a voltagechange in dicated at AV in FIG. 6. For example, the potential or voltageat the terminal 272 may decrease suddenly from a voltage ofapproximately 10 volts which is positive with respect to the common ornegative conductor L1 to a valley voltage of approximately 3 volts whichis positive with respect to the common or negative conductor N1, whenthe transistor Q4 breaks over during the charging of the capacitor C3.It is to be noted that prior to the break-over of the transistor Q4, thevoltage across the capacitor C3 will increase due to the chargingcurrent from the first current circuit means 210 to approximately thevoltage at the terminal 272 which may, for example, be approximately 10volts which is positive with respect to the common conductor N1 less thetwo forward voltage drops across the diode D28 and the baseemittercircuit of the transistor Q7 or the voltage across the capacitor C3 maybe approximately 9.4 volts prior to the breakover of the transistor Q4.When the transistor Q4 breaks over and the voltage at the terminal 272suddenly decreases to the valley voltage V of the transistor Q4, thevoltage at the terminal 282 at the right side of the capacitor C3 willchange correspondingly in a negative direction since there is no lowresistance discharge path provided for the capacitor C3. The voltage atthe terminal 282 will, for example, change in a negative direction to avalue which is equal for example to a voltage of 3 volts which ispositive with respect to ground less 9.4 volts which is the voltageacross the capacitor C3, for example, giving a voltage which isapproximately equal to 6.4 volts which is instantaneously negative withrespect to the common or negative conductor N1. The diode D28 will thenbe reverse biased or blocked and the transistor Q7 will be actuated to asubstantially cutoff or nonconducting condition. When the voltage at theright side of the capacitor C3 changes in a negative direction to avoltage value which is negative with respect to the voltage at thecommon or negative conductor N1, the right side of the capacitor C3 willthen be charged from the positive conductor P1 through the resistor R11with the charging current flowing through the emitter and the lower baseof the transistor Q4 to the common or negative conductor N1 of the powersupply input circuit 100. The voltage at the terminal 282 will increasein a positive direction until the diode D28 is forward biased and thecurrent in the base-emitter circuit of the transistor Q7 actuates thetransistor Q7 to a saturated condition. It should be noted that thetransistor Q4 will be held in a substantially conducting condition inthe emitter-lower base circuit of the transistor Q4 by the chargingcurrent which flows from the positive conductor P1 to the right side ofthe capacitor C3 until the diode D28 becomes forward biased and thetransistor Q7 is actuated to a saturated condition. When the transistorQ4 is no longer held in a substantially conducting condition in theemitter-lower base circuit, the transistor Q4 will be reset to asubstantially nonconducting condition in the emitterlower base circuit.The current from the collector of the transistor Q of the first circuitmeans 210 is not sufficient to maintain the transistor 04 in asubstantially conducting condition by itself because of the resistor R9which is connected in series with the emitter of the transistor Q5.

As shown graphically in FIG. 5, the voltage at the terminal 272 which isillustrated in graph A of FIG. 5 by the voltage waveform 930 increasesin a substantially linear manner, assuming that the highest phasevoltage across the resistors R1, R2 and R3 remains at a particularvalue, until the voltage at the terminal 272 reaches the peak pointvoltage V,.. When the transistor Q4 breaks over, the voltage at theterminal 272 suddenly decreases to the valley voltage V of thetransistor Q4 and the voltage at the terminal 272 remains at the valleyvoltage V until the right side of the capacitor C3 is charged from thepositive conductor P1 to a value sufficiently positive to forward biasthe diode D28 and actuate the transistor T7 to a saturated condition, asindicated by the voltage waveform 940 in graph B of FIG. 5 whichindicates the voltage at the terminal 282 of the pulse generatingcircuit 230. As shown in graph B of FIG. 5 by the voltage waveform 940,when the transistor Q4 breaks over, the voltage at the terminal 282suddenly changes in a negative direction by an amount equal to thedifierence between the peak point voltage and the valley voltage of thetransistor Q4 as indicated at AV in graph B of FIG. 5. Prior to thebreakover the transistor Q4, the voltage at the terminal 282 is held orclamped as indicated at the voltage V,, which is equal to the forwardvoltage drops of the diode D28 and the base-emitter circuit of thetransistor Q7 which is then in a substantially saturated condition. Asshown in graph B of FIG. 5, the voltage at the terminal 282 recoversfrom the predetermined negative value to which it is changed when thetransistor Q4 breaks over to a value which is sufiiciently positive, asindicated at V to forward bias the diode D28 and to actuate thetransistor Q7 to a substantially saturated condition. The time intervalrequired to charge the right side of the capacitor C3 at the terminal282 following the breakover of the transistor 04 is determined by thetime constant of the resistor-capacitor combination which includes thecapacitor C3 and the resistor R11 when charged from the positiveconductor P1. Referring to graph C of FIG. 5, the collector current ofthe transistor Q7 is indicated by the pulses of current 950 whichillustrate that the transistor O7 is substantially saturated prior tothe breakover of the transistor Q4 and that the transistor Q7 isrendered substantially nonconducting when the transistor 04 breaks overand is held in a substantially nonconducting or cutotf condition untilthe voltage at the terminal 282 recovers from the negative value towhich it is changed by the breakover of the transistor 24 to a valuewhich is sufficiently positive with respect to the common conductor N1to forward bias the diode D28 and to actuate the transistor O7 to asubstantially saturated condition. When the transistor 07 is renderedsubstantially nonconducting or cutoff following the breakover of thetransistor Q4, the unidirectional output current at the collector of thetransistor Q6 of the second current circuit means 220 is diverted fromthe collectorernitter bath of the transistor O7 to a current path whichincludes the diode D30 and will be applied to charge the timing orintegrating capacitor C4 when permitted to do so by the operation of thelevel detecting circuit 260, as will be explained hereinafter. Thepulses of current which are diverted from the emitter-collector circuitof the transistor Q7 to the current path which includes the diode D30 isillustrated graphically by the pulses of output current 960 shown ingraph D of FIG. 5. The magnitude or amplitude of the pulses of outputcurrent which are periodically available from the collector of thetransistor Q6 will vary in a substantially linear manner with thehighest of the unidirectional voltages across the resistors R1, R2 andR3 and, in turn, with the highest of the line currents which flow in theline conductors L1, L2 and L3, respectively. Since the time required tocharge the capacitor C3 and periodically break-over the transistor Q4will also vary in a substantialy linear manner or bedirectly-proportional to the output unidirectional current of the firstcurrent circuit means 210 at the collector of the transistor Q5, thefrequency or repetition rate of the current pulses 960 would also varyin a substantially linear manner with the highest of the unidirectionalvoltages across the resistors R1, R2 and R3 and, in turn, with thehighest line current which flows in the conductors L1, L2 and L3,respectively. It is also to be noted that the periodic pulses of outputcurrent 960 which are applied from the collector of the transistor O6 tothe current path which includes the diode D30 occur atthe end of eachsawtooth voltage waveform which is produced or generated by the pulsegenerating circuit and that the duration of the pulses is determined bythe time required to charge the right side of the capacitor C3 from theregulated voltage at the positive conductor P1 through the resistorR1 1. The duration or time width of the periodic output pulses ofcurrent 960 on the pulse generating circuit 230 will therefore remainsubstantially constant or at a predetermined value'since the width willbe substantially independent of variations in the line currents whichflow in the line conductors L1, L2 and L3 and the correspondingunidirectional voltages across the resistors R1, R2 and R3. When thepulse generating circuit 230 is permitted to charge the timing orintegrating capacitor C4 by the operation of the level detector circuit260 as will be explained hereinafter, the average current into thecapacitor C4 will vary in a substan tially linear manner with both thefrequency and the magnitude or amplitude of the pulses of output current960 which flow from the collector of the transistor Q6 through the diodeD30 as just described and therefore the net current into the capacitorC4 will vary substantially with the square of the highest unidirectionalvoltage across the resistors R1, R2 and R3 and, in turn, with the squareof the highest line current flowing in the conductors L1, L2 and L3.

More specifically, the time required to charge the capacitor C3 from thevalley voltage V,, to the peak point voltage V, from the output currentof the first current circuit means 210 at the collector of thetransistor Q5 is indicated at t in graph A of P16. 5. As illustrated ingraph A of FIG. 5, the difference between the peak point voltage and thevalley voltage of the transistor O4 is indicated as AV. It is well knownthat the relationship between the instantaneous voltage and theinstantaneous charge on the capacitor C3 is expressed by the followingformula: V Q/C3 where V is the voltage across the capacitor C3 and Q isthe instantaneous charge on the capacitor C3. The change in voltageacross the capacitor C3 which corresponds to the change in charge acrosssaid capacitor may be expressed as the following equation: V V C3 Q,),where Q equals the charge on the .capacitor C3 corresponding to thevoltage, V -V and O1 is the charge on the capacitor C3 corresponding tothe voltage, VrV Assuming that the highest unidirectional voltage acrossthe resistors R1, R2 and R3 remains at substantially a predeterminedvalue during the charging of the capacitor C3 from the valley voltage tothe peak point voltage of the transistor Q4, the unidirectional outputcurrent from the first current circuit means 210 will remain atsubstantially a predetermined or constant value at the collector of thetransistor Q and the rate of change of the charge across the capacitorC3 due to the output current from the collector of the transistor Q5will also remain at a substantially predetermined value. Based upon theabove assumption, the relationship between the charge on the capacitorC3 which corresponds to the voltage,- V,.-V the charge across thecapacitor C3 which corresponds to the voltage, V z-"V and the timeinterval 1 which is required to increase the charge across the capacitorC3 from the value which corresponds to the voltage, V,V,, to the valuewhich corresponds to the voltage, V V of the transistor Q4 is asfollows: Q Q =1, t,, where O is the charge on the capacitor C3 whichcorresponds to the voltage, V V O1 is the charge on the capacitor C3which corresponds to the voltage V -V I is the unidirectional outputcurrent from the first current circuit means 210 at the collector of thetransistor Q5 for a particular value of the highest phase voltage acrossthe resistors R1, R2 and R3 and t is the time required to charge thecapacitor C3 from the charge Q, to the charge 0,. Substituting intheprevious equation, V V l t,/C3. Since V V, V AV =1, t,/C3). Aspreviously explained, I V /R9 where V equal the'highest unidirectionalvoltage across the resistors R1, R2 and R3. Rearranging the aboveequation and substituting for 1,, t, C3AV R9/V In other words, the timerequired to charge the capacitor C3 from the valley voltage to the peakpoint voltage of the transistor Q4 which, in turn, determines thefrequency of the output pulses of current of the pulse generatingcircuit 230 varies directly with the value of the capacitor C3, thedifference AV between the valley voltage and the peak point voltage ofthe transistor Q4, and the value of the resistor R9 and varies inverselywith the highest unidirectional voltage V across the resistors R1, R2and R3. Similarly, the time interval required to charge the right sideof the capacitor C3 at the terminal 282 when the transistor Q4 breaksover, as indicated at t in graph D of FIG. 5, may be calculatedaccording to the following equation: I, C3AV Rll/V This equation isbased upon the assumption that the charging current which flows to theright side ofthe capacitor C3 is substantially a predetermined orconstant value dueto.

the fact that the'voltage at the positive conductor P1 is relativelymuch greater than the difference AV between the valley voltage and thepeak point voltage of the transistor Q4. As previously indicated, themagnitude or amplitude of the output pulses of current flowing into thetiming capacitor C4 when permitted to do so by the operation of thelevel detecting circuit 260, as will be explained hereinafter, may beexpressed by the following relationship: I V /(R38 R13),

where is the magnitude or the amplitude of the current pulses flowinginto the capacitor C4 through the diode D3!) when permitted to do so bythe operation of the level detecting circuit 260, V is the highestunidirectional voltage across the resistors R1, R2 and R3, and R38'andR13 are the values of the resistors R38 and R13 which are connected inseries with the emitter of the transistor Q6 at the input of the secondcurrent circuit means 220, as previously explained. Assuming that thetime interval 1, is relatively much greater than the time dura- V (R38R13) Rearranging the above equation, 1,. V

R9(R38=R13)V, It is important to note that the average current appliedto the timing or integrating capacitor C4 by the pulse generatingcircuit 230 when permitted to do so by the level detecting circuit 260is independent of the value of the capacitor C3 and is also independentof AV both of which may be difi'icult parameters to control in apractical application. In other words, the average current applied tocharge the capacitor C4 by the pulse generating circuit 230 whenpermitted to do so by the operation of the level detecting circuit 260varies substantially inversely with the square of the highestunidirectional voltage across the resistors R1, R2 and R3 and, in turn,with the square of the highest line current flowing in the conductorsL1, L2 and L3.

In summary, the pulse generating circuit 230 operates to produceperiodic pulses of output current to charge the capacitor C4 whenpermitted to do so by the operation of the level detectingv circuit 260with both the frequency or repetition rate and the magnitude or theamplitude of the pulses of output current varying in a substantiallylinear manner with the highest line'current flowing in the lineconductors L1, L2 and L3 and with the time duration or width of saidoutput pulses being maintained at substantially predetermined orconstant value by the operation of the pulse generating circuit 230, asjust described. As indicated above the time duration of each of theoutput pulses 960 as indicated graphically in graph 8 of FIG. 5, and asindicated by the above equation for t, is

substantially independent of variations in the line currents and thecorresponding unidirectionalvoltages across the resistors R1, R2 and R3but varies substantially inversely with the regulated voltage at thepositive conductor'P,. As previously explained, the output pulses ofcurrent are obtained from the output current of the second currentcircuit means 220 which is diverted away from the collector-emitter pathof the transistor Q7 periodically and is directed into the current pathwhich includes the diode D30 when the transistor O7 is actuated to asubstantially nonconducting or cutoff condition periodically by thepulsegenerating circuit 230. It is important to note that since the capacitorC3 is involved in the R-C time constant which for a particular value ofthe highest voltage across the resistors R1, R2 and R3 determines thecharging time from the valley voltage V, to the peak point voltage V Pat the left side of the capacitor C3, any change in the value of thecapacitor C3 due to changes in environmental temperature or for someother cause would vary the frequency or repetition rate of the outputpulses of current from the pulse generating circuit 230. Since however,the capacitor C3 also forms part of the R-C time constant which with theunidirectional voltage between the conductors P1 and N1 determines thecharging time to the capacitor C3 from the conductor P1 through theresistor R11 after the unijunction transistor Q4 breaks over, any changein the value of the capacitor C3 would also result in an ofi'setting orcompensating change in the duration or time width of the output pulsesof the pulse generating circuit 230 which would exactly compensate forany variations in the value of the capacitor C3 and the correspondingefiect on the average value of the output pulses of current from thepulse generating circuit 230 which charges the timing or integratingcapacitor C4 when permitted to do so by the level detecting circuit 260.

Similarly, if the peak point voltage (V and the valley voltage (Vcharacteristics of the unijunction transistor Q4 should vary or changedue to environmental conditions or for some other cause, the frequencyof the output pulses of current from the pulse generating circuit 230would change correspondingly but the duration or time width of theoutput pulses would also change correspondingly in an offsetting mannerto thereby compensate for the changes in the characteristics of theunijunction transistor 04.

In general, the level detecting circuit 260 of the long time delaytripping circuit 200 is connected to the second auctioneering circuit120 and to the timing or integrating capacitor C4 to respond to thehighest instantaneous voltage across the resistors R1, R2 and R3 and, inturn, to the highest of the line currents in the conductors L1, L2 andL3 to permit the pulse generating circuit 230 to start charging thetiming capacitor C4 when the highest instantaneous line current in theconductors L1, L2 and L3 reaches a predetermined value as described ingreater detail and claimed in a copending application Ser. No. 765,582filed concurrently with this application by J. D. Watson and which isassigned to the same as signee as this application. The level detectingcircuit 260 includes the PNP transistors Q8 and Q9 which are connectedto control the conducting state of a PNP transistor Q10 which isconnected to normally divert the output pulses of current from the pulsegenerating circuit 230 away from the timing capacitor C4 to the commonor negative conductor N1.

More specifically, the input circuit of the level detecting circuit 260comprises a voltage dividing network which includes the rheostat orvariable resistance means R39, the resistor R14 and the resistor R15which are connected in series with one another, the series circuit beingconnected between the variable voltage output conductor V1 of the firstauctioneering circuit 110 and the positive conductor P3 which providesone of the regulated, unidirectional output voltages from the powersupply input circuit 100. It is important to note that theunidirectional voltage at the variable voltage conductor V1 variesinstantaneously with the highest of the unidirectional voltages acrossthe resistors R1 and R2 and R3, since the voltage at the conductor V1 isnot filtered by the capacitor C1, as is the output voltage at thevariable voltage conductor V2. The base of the transistor T8 isconnected to the junction point between the resistors R14 and R15 whilethe emitter of the transistor O8 is connected to the positive conductorP1. The diode D29 is connected between the base and the emitter of thetransistor O8 to limit the inverse voltage which is ap plied between theemitter and the base of the transistor Q8, when the transistor Q8 issubstantially nonconducting or cutoff and to prevent the base-emittercircuit of the transistor Q8 from breaking down under the inversevoltage which'might otherwise be applied to the base-emitter circuit ofthe transistor Q8. The collector of the transistor Q8 is connected tothe common or negative conductor N1 through the col1ec-,

tor load resistor R16. The transistor O9 is directly coupled to theoutput of the transistor Q8, since the base of the transistor Q9 isconnected to the collector of the transistor Q8, while the emitter ofthe transistor Q9 is directly connected to the positive conductor P1.The collector of the transistor O9 is connected to the common ornegative conductor N1 through the collector load resistor R17. Thecapacitor C5 is connected between the emitter and the collector of thetransistor Q9 to cooperate with the resistor R17 to delay the resettingof the level detecting circuit 260 as will be explained hereinafter. Thetransistor Q10 is directly coupled to the transistor Q9 with thecollector of the transistor Q9 being directly connected to the base ofthe transistor Q10. The collector of the transistor 010 is directlyconnected to the common or negative conductor N1, while the emitter ofthe transistor Q10 is connected to the positive conductor P3 through aseries circuit which includes the forward connected diode D35, theforward connected diode D46 and the resistor R of the output circuit 400and the forward connected diode D45 of the output circuit 400. Theresistor R18 is connected between the base and the emitter of thetransistor 010 to decrease the sensitivity of operation of thetransistor Q10 and to establish the minimum base-emitter currentnecessary to actuate the transistor Q10 to a saturated condition.

In the operation of the level detecting circuit 260, when the highestinstantaneous line current flowing in the conductors L1, L2 and L3 isless than substantially a predetermined value and the correspondinghighest instantaneous unidirectional voltage across the resistors R1, R2and R3 is less than a substantially predetermined voltage, thetransistor Q8 of the level detecting circuit 260 is actuated to asaturated condition since the emitter-base circuit of the transistor Q8is forward biased and a base drive current flows from the positiveconductor P1 through the emitter-base circuit of the transistor 08 andthe resistor R15 to the positive conductor P3. When the transistor Q8 isin a normally saturated condition, the voltage drop across the resistorR15 due to the current which flows through the rheostat R39 and theresistor R14 and the current which flows in the emitter-base circuit ofthe transistor Q8 is equal to the voltage difference between theconductors P1 and P3 less the forward voltage drop across theemitter-base circuit of the transistor Q8. For example, if theunidirectional voltage at the conductor P1 is 33 volts positive withrespect to the common conductor N1 and the voltage at the conductor P3is 16.5 volts positive with respect to the common conductor N1, thevoltage across the resistor R15 will be 16.5 volts less the forwardvoltage drop across the emitter-base circuit of the transistor Q8 orapproximately 16 volts. In other words, when the transistor O8 is in anormally saturated condition, the voltage at the base of thetransistor'QS will difi'er from the voltage at the positive conductor P1only by the forward voltage drop of the emitter-base circuit ofthetransistor Q8. The sumof the instantaneous voltage drops across therheostat R39 and R13 will be substantially equal to the highest of theunidirectional voltages across the resistors R1, R2 and R3, sincethe'forward voltage drop across one of thediodes D17, D18 or D19 willsubstantially compensate for the forward voltage drop across theemitter-base circuit of the transistor Q8 and will assist in temperaturecompensating for the variations which may occur in the forward voltagedrop across the emitter-base circuit of the transistor Q8 due to thechanges in the environmental temperature. Since the'sum of the voltagedrops across the rheostat R39 and R13 is substantially equal to thehighest of the unidirectional voltages across the resistors R1, R2 andR3, the current flowing through the rheostat R39 and the resistor R14will be equal to the highest unidirectional voltage across the resistorsR1, R2 and R3 divided by the sum of the resistances of the rheostat R39and the rheostat R14. As the highest unidirectional voltage across theresistors R1, R2 and R3 increases prior to reaching the predeterminedvoltage, previously mentioned, the current which flows through therheostat R39 and the resistor R14 increases while the current whichflows through the emitter-base circuit of the transistor Q8 decreases.This is because the voltage across the resistor R15 is constrained to beequal to the voltage difference between' the conductors P1 and P3 lessthe forward voltage drop across the emitter-base circuit of thetransistor Q8 as long as said transistor remains in a saturatedcondition, as previously ex+ plained.

As long as the transistor Q8 remains in a saturated condition, thecurrent which flows in the resistor R16 will be diverted to theemitter-collector circuit of the transistor Q8 and maintain thetransistor Q9 in a substantially nonconducting or cutoff condition. Aslong as the transistor Q9 is maintained in a substantially nonconductingor cutoff condition, the current flow through the emitter-collectorcircuit of the transistor Q9 will be substantially negligible and thevoltage drop across the resistor R17 due to the emitter-collectorcurrent of the transistor Q9 will be also substantially negligible. Thevoltage at thebase of the transistor Q10 will therefore be at a valuewhich is relatively close to the voltage of the common or negativeconductor N1 and a base drive current will flow from the positiveconductor P3 through the series circuit which includes the diode D45,the resistor R35, the diode D46, the diode D35, the emitter-base circuitof the transistor Q and the resistor R17 to the common or negativeconductor N1. The transistor Q10 will therefore be normally maintainedin a saturated condition to thereby provide a low resistance currentpath from the upper side of the timing or integrating capacitor C4through the forward connected diode D31, the forward connected diode D35and the emitter-collector circuit of the transistor Q10 to the common ornegative conductor N1 to thereby prevent the output pulses of currentsfrom the pulse generating circuit 230 from cumulatively charging thetiming capacitor C4. It is to be noted that in the normal operatingcondition of the level detecting circuit 260, as long as the highestline current flowing in the conductors L1, L2 and L3 remains below apredetermined value and the corresponding highest unidirectional voltageacross the resistors R1, R2 and R3 remains below a correspondingpredetermined voltage value, the transistor Q9 will remain in asubstantially nonconducting or cutoff condition and the capacitor'C5will charge to a voltage which is substantially equal to the voltagedifference between the positive conductor P1 and the common or negativeconductor N1 less a relatively small voltage drop across the resistorR17.

When the highest line current flowing in the conductors L1, L2 and L3exceeds or increases to a value above the predetermined value to whichthe level detecting circuit 260 responds and the highest unidirectionalinstantaneous voltage across the resistors R1, R2 and R3 exceeds acorresponding predetermined voltage value, the current through therheostat R39 and the resistor R14 increases while the transistor Q8 isstill in a saturated condition until the current the emitter-basecircuit of the transistor Q8 decreases toa negligible value and thetransistor O8 is actuated to a substantially nonconducting or cutoffcondition. It is to be noted that the predetermined highestinstantaneous current in the line conductors L1, L2 and L3 at which thetransistor O8 is actuated to a substantially nonconducting condition maybe adjusted by the setting of the rheostat R39. When the transistor O8is actuated to a substantially nonconducting condition, the current inthe emitter-collector path of the transistor Q8 decreases to asubstantially negligible value and the current which flows in theresistor R16 now flows from the positive conductor Pl through theemitter-base circuit of the transistor Q9. The transistor Q9 thencarries saturated current in the emitter-collector circuit of thetransistor Q9 to increase the voltage drop. across the resistor R17 whenthe voltage at the base of the transistor Q10 increasing to a valuewhich is substantially equal to the voltage at the emitter of thetransistor Q10 to thereby remove the forward bias from the emitter-basecircuit of the transistor Q10 and to'actuate the transistor Q10 to asubstantially nonconducting or cutoff condition. When the transistor Q10which forms the control means 270 is actuated to a substantiallynonconducting condition, the low resistance path between the upper sideof the timing capacitor C4 and the common conductor N1 through thediodes D31 and D35 is operatively removed and the timing capacitor C4 isthen permitted to accumulate a charge from the output of the pulsegenerating circuit 230 with the voltage across the timing capacitor C4increasing in accordance with substantially the square of the highestunidirectional voltage across the resistors R1, R2 and R3 and, in turn,with the highest line current flowing through the line conductors L1, L2and L3.

When the transistor O9 is actuated to a substantially saturatedcondition in response to the predetermined overload current flowing inone of the line conductors L1, L2 and L3, the capacitor C5 which waspreviously charged up to a voltage equal to the difference in voltagebetween the conductors P1 and N1 less the voltage drop across theresistor R17 will rapidly discharge through the transistor Q9 and morespecifically through the emitter-collector path of the transistor Q9until the capacitor C5 is substantially completely discharged. If thehighest load current flowing in the line conductors L1, L2 and L3 andthe corresponding highest unidirectional voltage across the resistorsR1, R2 and R3 should decrem to a value below the predetermined orthreshold value afier the level detecting circuit 260 has operated toactuate the transistor Q10 to a substantially nonconducting condition,the transistor Q8 will be restored to a substantially saturatedcondition and the transistor Q9 will be returned to a substantiallynon-conducting condition. Since the sum of the voltage drops across thecapacitor C5 and the resistor R17 is equal to the voltage differencebetween the conductors P1 and N1, the voltage across the capacitor C5following its discharge by the actuating of the transistor Q9 to asubstantially saturated condition will increase relatively slowly afterthe transistor O9 is restored to a substantially nonconducting conditiondue to the presence of the resistor R17 in the charging path of thecapacitor C5. The charging current which flows to the capacitor C5 afterthe transistor 09 is returned to a substantially nonconducting conditionwill produce a gradually decreasing voltage drop across the resistor R17which is sufficient to maintain the transistor Q10 in a substantiallynonconducting condition for a predetermined time delay after the highestinstantaneous unidirectional voltage across the resistors R1, R2 and R3decreases below the predetermined value necessary to actuate the leveldetecting circuit 260. In other words, if the highest instantaneous linecurrent flowing in the line conductors L1, L2 and L3 should exceed apredetermined overcurrent value and then instantaneously decrease belowthe predetermined instantaneous value, the transistor Q10 will bemaintained in a substantially nonconducting condition by the timingcircuit which includes the capacitor C5 and the resistor R17 which willdelay the resetting of the level detecting circuit 260 for apredetermined time delay which may, for example, be slightly longer thanthe time duration of one-half cycle of the alternating current whichflows in the line conductors L1, L2 and L3. If the highest of theinstantaneous line currents which flow in conductors L1, L2 and L3should exceed the predetermined overload current to which the leveldetecting circuit 260 responds and then instantaneously decrease for aperiod of time less than the time delay for which the level detectingcircuit 260 is set the transistor Q10 will be maintained in asubstantially nonconducting condition to permit the timing capacitor C4to continue accumulating charge from the output pulses of current fromthe pulse generating circuit 230, but if the time interval betweensuccessive periods of instantaneous overcurrent should exceed the timedelay period for which the level detecting circuit 260 is set, thetransistor Q10 will be restored to a substantially saturated conditionand rapidly reset the timing capacitor C4 by discharging the timingcapacitor C4 through the circuit which includes the diodes D31 and D35and the emitter-collector circuit of the transistor Q10 to thereby resetthe timing capacitor C4 so that the time delay provided by the overalllong time delay tripping circuit 200 would have to again start from aninitial operating point on the timing capacitor C4.

In summary, the level detecting circuit 260 as described in thecopending application previously mentioned, provides a relatively fastresetting time since the level detecting circuit 260 responds to theinstantaneous value of the highest unidirectional voltage across theresistors R1, R2 and R3 and, in turn, to the highest instantaneous linecurrent flowing in the line conductors L1, L2 and L3 and resets thetiming capacitor C4 if the time interval between successiveinstantaneous periods of overcurrent above the predetermined value forwhich the level detecting circuit 260 is adjusted is longer than thepredetermined time period which may, for example, be slightly longerthan onehalf cycle of the alternating current flowing in the conductorsL1, L2 and L3. It is to be noted that the predetermined overcurrentlevel to which the level detecting circuit 260 responds is relativelylower normally than the instantaneous overload current to which theinstantaneous tripping circuit 300 responds, as will be describedhereinafter. It is also to be noted that when the transistor Q10 whichforms the control means 270 is in a substantially saturated condition,the diode D31 is forward biased and the output pulses of current fromthe pulse generating circuit 230 which flows from the collector of thetransistor Q6 will flow to the common conductor N1 through a currentpath which extends from the collector of the transistor Q6 through thediodes D30 and D31, the diode D35, and the emitter-collector path of thetransistor Q10. Whenever the transistor Q is actuated to a substantiallynonconducting or cutoff condition, the voltage applied to the cathode ofthe diode D31 from the positive conductor P3 through the diode D45, theresistor R35 and the diode D46 will be sufficient to reverse bias thediode D31 and permit the timing capacitor C4 to accumulate charge fromthe output pulses of current from the pulse generating circuit 230 whichflow from the collector of the transistor Q6 through the diode D30 tothe upper side of the timing capacitor C4.

In the overall operation of the long time delay tripping circuit 200,when the capacitor C4 is permitted to charge from the output pulses ofcurrent of the pulse generating circuit 230, the voltage across thecapacitor C4 increases in discrete steps until the voltage at the upperside of the capacitor C4 is sufficiently positive to forward bias thediode D31. When the diode D31 is forward biased by the voltage at theupper side of the capacitor C4 increasing to a predetermined orthreshold value, the output pulses of current from the collector of thetransistor Q6 are applied through the diodes D30 and D31 to the outputcircuit 400, as will be explained hereinafter, to actuate the operationof the output circuit 400 to energize the trip coil 36 of the circuitbreaker CB to thereby actuate the opening of said circuit breaker. Sincethe average charging current applied to the timing capacitor C4 from thepulse generating circuit 230 when the pulse generating circuit 230 ispermitted to charge the capacitor C4 is substantially proportional tothe square of the highest unidirectional voltage across the resistorsR1, R2 and R3 and, in turn, to the highest line current flowing in theconductors L1, L2 and L3, the time delay required to charge thecapacitor C4 to substantially a predetermined or threshold voltagesufficient to actuate the output circuit 400 varies substantiallyinversely with the square of the highest line current which flows in theconductors L1, L2 and L3. In order to limit the necessary size of thetiming capacitor C4 to a practical value which is sufficient to providethe time delay required for different values of overload currents, themagnitude of the output unidirectional current pulses from thetransistor O6 is limited to a certain range of current values. Undercertain operating conditions, such as relatively lower overloadcurrents, the unidirectional output pulses of current at the collectorof the transistor Q6 which are applied through the diodes D30 and D31when the voltage across the capacitor C4 reaches the predetermined orthresholdvalue, may not be sufficient to actuate the operation of theoutput circuit 400.

In order to increase the sensitivity of ,the long time delay trippingcircuit 200 and to insure that the output pulses of current applied fromthe long time delay tripping circuit 200 to actuate the output circuit400 are sufficient for all operating conditions required in a particularapplication, the auxiliary pulse generating circuit 240 is connected tothe pulse generating circuit 230 to periodically increase the voltageavailable at the upper side of the timing capacitor C4. Morespecifically the auxiliary pulse generating circuit 240 is provided toperiodically increase the voltage between the lower side of the timingcapacitor C4 and the common or negative conductor N1.

More specifically, the auxiliary pulse generating circuit 240 comprisesa N PN transistor Q3. The base of the transistor Q3 is connected to thepositive conductor P1 through the resistor R7 and is coupled to theupper base of the unijunction transistor 04 of the pulse generatingcircuit-230 by the capacitor C2, while the emitter of the transistor O3is directly connected to the common or negative conductor N1. Thecollector of the transistor 03 is connected to the positive conductor Plthrough the collector load resistor R8 and also to the lower side of thetiming capacitor C4. It is to be noted that the diode D34 is connectedbetween the lower side of the timing capacitor C4 and the common ornegative conductor N1 to complete the discharge path for the timingcapacitor C4 during the actuation of the output circuit 400 by the longtime delay tripping circuit 200, as will be explained hereinafter. Thediode D32 which may comprise one or more diodes as required in aparticular application is connected between the collector of thetransistor Q3 and the common or negative conductor N1 to limit themagnitude of the output pulses of voltage from the auxiliary pulsegenerating circuit 240 to the forward voltage drop of the diode D32.

In the operation of the auxiliary pulse generating circuit 240, thetransistor Q3 is normally maintained in a substantially saturatedcondition by the base drive current which flows from the positiveconductor Pl through the resistor R7 and the base emitter circuit of thetransistor Q3 to the negative or common conductor N1. When thetransistor Q3 is in a substantially saturated condition, the lower sideof the timing capacitor C4 is at substantially the same potential as thecommon or negative conductor N1, since the voltage drop across thecollector-emitter circuit of the transistor Q3 is substantiallynegligible when the transistor Q3 is in a substantially saturatedcondition. When however the unijunction transistor Q4 of the pulsegenerating circuit 230 periodically breaks over during the operation ofthe pulse generating circuit 230, a negative voltage pulse is producedat the upper base of the transistor Q4 each time that the transistor Q4breaks over and this negative voltage pulse is transmitted or coupled tothe base of the transistor Q3 to substantially a nonconducting or cutoffcondition. When the transistor Q3 is periodically actuated to asubstantially nonconducting condition by operation of the pulsegenerating circuit 230, the voltage at the collector of the transistorQ3 increases in a positive direction and raises the voltage at the lowerside of the timing capacitor C4 by an amount equal to the forwardvoltage drop of the diode D32. In the overall operation of the long timedelay tripping circuit 200, as the charge on the timing capacitor C4approaches the predetermined or threshold value necessary to forwardbias the diode D31, the auxiliary or supplementary periodic outputvoltage pulses applied at the lower side of the capacitor C4'effectivelyincreases the voltage at the upper side of the capacitor C4 with respectto the common or negative conductor N1 and permits the output pulse ofcurrent from the collector transistor Q6 to be applied through the diodeD31 when the total voltage effective at the upper side of the capacitorC4 reaches the predetermined or threshold value necessary to actuate theoutput circuit 400. The operation of the output circuit 400 is thusassured over the entire range of overload currents to which the longtime delay tripping circuit 200 responds. It is to be noted that thediode D27 is connected between the base and the emitter of thetransistor Q3 for the purpose of limiting the voltage change at the leftsideof the capacitor C2 when the transistor Q3 is periodically actuatedto a nonconducting condition to thereby assist in controlling the widthof the output pulses at the collector of the transistor Q3 andprotecting the base-emitter circuit of the transistor Q3 from excessivereverse bias voltages.

OUTPUT CIRCUIT 400 In general, the output circuit 400 of the protectivedevice shown in FIG. 1 is connected to the long time delay trippingcircuit 200 to respond to substantially a predetermined charge on thecapacitor C4 which corresponds to a predetermined or threshold voltageacross said capacitor to actuate the men gization of the trip coil 36 ofthe circuit breaker CB following a predetermined time delay after theoperation of the level detecting circuit 260 permits the timingcapacitor C4 to start accumulating the charge. More specifically theoutput circuit 400 comprises an output level detecting circuit 410 whichis connected to the timing capacitor C4 through the diode D31, thesemiconductor switching device Q17 whose operation is actuated by theoutput level detecting circuit 410 and the auxiliary potential source420 which is provided to maintain certain operating potentials duringcertain operating conditions, as will be explained hereinafter.

The output level detecting circuit 410 is of the breakover type in thatonce the operation of the output level detecting circuit 410 isinitiated, the operation of said circuit continues or proceeds byregenerative action until the operation of said circuit is completed.The output level detecting circuit 410 comprises the PNP transistor Qand the NPN transistor Q16. The emitter of the transistor Q15 isconnected to the upper side of the timing capacitor C4 through the diodeD31, while the base of the transistor Q15 is connected to the positiveconductor P3 through the resistor R35 and the forward connected diodeD45. The collector of the transistor Q15 is connected to the base of thetransistor Q16 through the diode D47 and also to the control means 150of the power supply input circuit 100 through the isolating diode D48 inorder to prevent the operation of the output circuit 400 in the eventthat the energy storing capacitor C13 of the power supply input circuit100'is not fully charged, as previously explained. As shown in FIG. 2,the collector of the transistor Q16 is directly connected to the base ofthe transistor Q15, while the emitter of the transistor Q16 is connectedto the common or negative conductor N1 through the resistor R34 and alsoto the gate electrode of the silicon controlled rectifier or switchingdevice Q17. The resistor R33 is connected between the emitter and thebase of the transistor Q15 in order to normally maintain the potentialat the emitter of the transistor Q15 at substantially the same potentialas at the base of the transistor Q15. In order to protect theemitter-base circuit of the transistor Q15 from excess reverse biasduring certain operating conditions, the diode D46 is connected betweenthe emitter and the base of the transistorQlS to limit the reversevoltage across the emitter-base circuit of the transistor Q15 to theforward voltage drop of the diode D46. The capacitor C11 is connectedbetween the emitter and the base of the transistor Q15 to provide somedegree of noise suppression in the operation of the output leveldetecting circuit 410 by by-passing transient voltage surges which mayoccur in the overall operation of the protective device shown in FIG. 1around the emitter-base circuit of the transistor Q15. The resistor R32is connected between the base of the transistor Q16 and the common ornegative conductor N1 to provide a shunt path around the base-emittercircuit of the transistor Q16 for the leakage current which might flowat relatively high environmental temperatures from the collector to thebase of the transistor Q16. The resistor R32 prevents the leakagecurrent from flowing from the base to the emitter of the transistor Q16and being amplified by the current gain of the transistor Q16 whichmight cause improper tripping operations due to the gating of thesilicon controlled rectifier Q17. The resistor R32 also determines theamount of current at the emitter of the transistor Q15 which isnecessary to actuate the operation of the output level detecting circuit410.

The auxiliary potential source 420 is connected to the output leveldetecting circuit 410 to temporarily maintain the voltage at the base ofthe transistor Q15 whenever the overall protective device shown in HO. 1is deenergized sufficiently long enough to prevent an improper operationof the output level detecting circuit400 when the voltages at thepositive conductors P1, P2 and P3 collapse at a relatively fast rate andthe voltage on the timing capacitor C4 might be sufficient to actuatethe operation of the output level detecting circuit 410 and to cause animproper tripping operation of the circuit breaker CB. The auxiliarypotential source 420 comprises the diode D45 which is connected betweenthe positive conductor P3 and the right end of the resistor R35, thecapacitor C12 which is connected between the junction point of theresistor R35 and the diode D45 and the common or negative conductor N1and the resistor R36 which is connected between the upper side of thecapacitor C12 and the common or negative conductor N1. lt is to be notedthat the resistor R36 provides a relatively slow discharge path for thecapacitor C12 after the overall protective device shown in FIG. 1 hasbeen deenergized for a certain time period and the auxiliary potentialsource 420 has performed its intended purpose. It is to be noted thatthe auxiliary potential source 420 also prevents improper trippingoperations in the event that the overall protective device should betemporarily energized due to a temporary loss of power.

In order to energize the trip coil 36 of the circuit breaker CB inresponse to the operation of the output level detecting circuit 410, theanode of the silicon controlled rectifier or semiconductor switchingdevice Q17 is connected to the posi' tive conductor Pl through theresistor R37, while the cathode of the silicon controlled rectifier Q17is connected to the commonor negative conductor N1. The trip coil 36 iselectrically connected in parallel with the resistor R37 between thepositive conductor P1 which, in turn, is connected to one side of thesupply capacitor C13 and the junction point between the resistor R37 andthe anode of the silicon controlled rectifier Q17. More specifically,the trip coil 36 is connected between the terminal 414 as shown in FIG.1 which, in turn, is connected to the positive conductor P1 and theterminal 422 which is connected, in turn, to the junction point betweenthe resistor R37 and the anode of the silicon controlled'rectifier Q17.In order to prevent an improper operation of the silicon controlledrectifier Q17 due to transient voltage surges which may occur during theoverall operation of the protected device shown in FIG. 1, a noisesuppression network, which includes the resistor R44 and the capacitorC17 connected in series, is connected between the anode and the cathodeof the silicon controlled rectifier Q17 to bypass transient voltagesurges around the silicon controlled rectifier Q17.

in the overall operation of the output circuit 400, when the leveldetecting circuit 260 of the long time delay tripping circuit 200permits the timing capacitor C4 to accumulate charge from the pulsegenerating circuit '230, the voltage across the timing'capacitor C4increases in discrete steps at a rate which varies substantially withthe square of the highest line current which flows in the conductors L1,L2 and L3, as previously explained, until the voltage across the timingcapacitor C4 is sufficient to forward bias the diode D31. When the diodeD31 is forward biased by the voltage at the upper side of the timingcapacitor C4 which'is periodically increased by the auxiliary pulsingcircuit 240, as previously explained, an input current for the outputcircuit 400 flows from the collector of the transistor Q6 through thediodes D30 and D31, through the emitter-base circuit of the transistorQ15 of the output level detecting circuit 410 to thereby increase thecurrent which flows from the emitter to the collector of the transistorQ15 and through the diode D47 through the baseemitter circuit of thetransistor Q16.'When the transistor Q16 starts to conduct current in itsbase-emitter circuit, the current which flows from'the collector to theemitter of the transistor Q16 also increases to thereby additionallyincrease the current flow from the emitter to the base of the transistorQ15. It is to be noted that the current which flows in thecollector-emitter path of the transistor Q16 also flows from thepositive conductor P3 through the diode D45 and the resistor R35 throughthe collector-emitter circuit of the transistor Q16 and to the commonconductor N1 through the resistor R34. The effect of the increase in thecollector-emitter current of the transistor Q16 and its consequenteffect on the emitter-base current of the transistor Q15 increases untilboth of the transistors Q15 and Q16 are actuated to a substantiallysaturated condition. The output current of the output level detectingcircuit 410 from the emitter of the transistor Q16 also flows throughthe gate of the silicon controlled rectifier Q17 into the anode of thesilicon controlled rectifier Q17 to thereby actuate the siliconcontrolled rectifier Q17 to a substantially conducting condition. Whenthe silicon controlled rectifier Q17 is actuated to a substantiallyconducting condition, the trip coil 36 is energized by the current whichflows from the positive conductor P1 through the trip coil 36 andthrough the anode-cathode circuit of the silicon controlled rectifierQ17 to the common or negative conductor N1 to thereby actuate a trippingoperation of the circuit breaker CB. It should be noted that the currentwhich energizes the trip coil 36 flows from the right side of thecapacitor C13 through the positive conductor P1, the trip coil 36 andthe anode-cathode circuit of the silicon controlled rectifier 017 to thecommon conductor N1 and then to the left side of the capacitor C13.

In the event that the capacitor C13 is not charged suffrciently toenergize the trip coil 36, the control means 150 will prevent theoperation of the output circuit 400 by providing a relatively lowresistance path from the collector to the transistor Q15 through thediode D48 which will then be forward biased and through thecollector-emitter circuit of the transistor Q2 of the control means 150to the common or negative conductor N1.

It is to be noted that after the trip coil 36 is energized by thedischarge of the capacitor C13 through said trip' coil and the siliconcontrolled rectifier Q17, the resistor R37 which is connected in serieswith the anode cathode circuit of the silicon controlled rectifier Q17provides a circulating path to dissipate the stored energy in the tripcoil 36 which normally involves an inductive device and thereby limitsthe inverse voltage applied to the silicon controlled rectifier Q17 to avalue within the rating of the silicon controlled rectifier Q17.

As previously mentioned, the auxiliary pulsing circuit 240 is providedto periodically increase the voltage at the lower side of the timingcapacitor C4 and in effect at the upper side of the timing capacitor C4in order to ensure that the input cur-,

rent applied to the output circuit 400 will be sufficient over theentire range of overload currents to which the long time delay trippingcircuit 200 is intended to respond.

Referring now to FIG. 4, the overall operation of the protective deviceshown in FIG. 1 is indicated graphically by a set of curves whichindicate the tripping time in seconds plotted as a function of thepercentage of rated current of the associated circuit breaker with bothvalues plotted on logarithmic scales. More specifically, the curves 822and 824 indicate the limiting curves of a family of curves whichillustrate the operation of the long time delay tripping circuit 200. Asindicated by the curves 822 and 824, the tripping time in seconds variessubstantially inversely with the square of the overcurrent over apredetermined range of overcurrents to which the long time delaytripping circuit 200 responds. The predetermined highest line currentwhich actuates the start of the time delay provided in the operation bythe long time delay tripping circuit 200 may be controlled between thelimits indicated by the vertical curves 810 and 812 by the setting ofthe rheostat R39 which forms part of the level detecting circuit 260 ofthe long time delay tripping circuit 200. The minimum time delaycharacteristic provided by the time delay tripping circuit 200, asindicated by the curve 822, may be obtained by the adjustment of therheostat R38 which forms part of the second current circuit means 220while the maximum time delay provided by the long time delay trippingcircuit 200 as indicated by the curve 824 may be similarly obtained bythe adjustment of the rheostat R38 with a family substantially parallelcurves being available between the limiting curves 822 and 824 by theadjustment of the rheostat R38. In other words, the long time delaytripping circuit 200 provides substantially an Pr K (where K equals aconstant and t equals tripping time) operating characteristic which maybe varied in a substantially continuous manner between' a minimum timedelay characteristic and a maximum time delay characteristic indicatedby the curves 822 and 824, respectively, by the adjustment of therheostat R38 which in effect varies the constant to which 1 issubstantially equal over a predetermined operating range of overloadcurrents. As previously explained, if the highest line current flowingin the conductors L1, L2 and L3 exceeds the predetermined current valueto which the level detecting circuit 260 responds as determined by thesetting of the rheostat R39, the timing capacitor C4 will be permittedto start accumulating a charge from the pulse generating circuit 230.If, however, the highest line current flowing in the line conductors L1,L2 and L3 then decreases to a value less than the predetermined value towhich the level detecting circuit 60 responds and remains less than thepredetermined value, the

timing capacitor C4 will be reset after a predetermined time interval ordelay which may be adjusted or selected to be slightly longer thanone-half cycle of the alternating current flowing in the line conductorcurrents L1, L2 and L3 assuming that the last-mentioned time intervalbefore reset of the capacitor C4 ends before the voltage across thecapacitor C4 is sufficient to actuate the output level detecting circuit410. The reset of the timing capacitor C4 will be accomplished byrestoring the control means 270 to substantially a saturated conditionwhich rapidly discharges the timing capacitor C4 at the end of the timeinterval just mentioned. It is to be noted that the control means 270 isof the emitter follower type.

INSTANTANEOUS TRIPPING CIRCUIT 300 Referring now to the instantaneoustripping circuit 300 indicated in block form in FIG. 1 and shown indetail in FIG. 2, the instantaneous tripping circuit 300, in general, isconnected between the first auctioneering circuit 110 of the powersupply input circuit and the level detecting circuit 410 of the outputcircuit 400 to actuate the energization of the trip coil 36 of thecircuit breaker CB when the highest instantaneous line current flowingin the conductors L1, L2 and L3 increases above or exceeds substantiallya predetermined or threshold value without any intentional time delay.

More specifically, the instantaneous tripping circuit 300 as shown inFIG. 2 comprises a PNP transistor Q18 and a voltage dividing networkwhich includes the rheostat R42, the resistor R24, and the resistor R89which are connected in series with one another between the variablevoltage output conductor V1 of the first auctioneering circuit and thepositive conductor P3. The emitter of the transistor Q18 is connected tothe junction point between the resistors R24 and R89, while the base ofthe transistor Q18 is connected to the positive conductor P2 in orderthat the forward voltage drop across the diode D23 which may include oneor more forward connected diodes in a particular application compensatethe input voltage of the instantaneous tripping circuit 300 for theforward voltage drop across one of the diodes D17, D18 or D19 of thefirst auctioneering circuit 110 and for the forward voltage drop acrossthe emitter-base circuit of the transistor Q18 during the operation ofthe instantaneous tripping circuit 300. The diode D39 is connectedbetween the emitter and the base of the transistor Q18 in order toprotect the emitter-base circuit of the transistor Q18 from excessivereverse bias by limiting the maximum reverse voltage applied to theemittenbase circuit of the transistor Q18 to the forward voltage drop ofthe diode D39. The collector of the transistor Q18 is connected to thecommon or negative conductor N1 by the collector load resistor R25. Theoutput of the instantaneous tripping circuit 30 at the collector of thetransistor Q18 is connected to the emitter of the transistor Q15 of theoutput level detecting circuit 410 by the isolating diode D40 whoseanode is connected to the collector of the transistor Q18 and whosecathode is connected to the emitter of the transistor Q15. The capacitorC8 is electrically connected in parallel to resistor R25 between thecollector of the transistor Q18 and the common or negative conductor N1in order to provide a degree of noise suppression in the operation ofthe instantaneous tripping circuit 300 by diverting the output of theinstantaneous tripping circuit 300 to the common conductor N1 when theoutput is due to transient voltage surges which may occur during theoperation of the overall protective device shown in FIG. 1 and also toprovide a pulse of discharge current to the output level detectingcircuit 410 of the output circuit 400 during the operation of theinstantaneous tripping circuit 300 to insure that the transistors Q15and Q16 are both actuated to substantially saturated conditions and toinsure that the silicon control rectifier 217 is actuated to asubstantially conducting condition to energize the trip coil 36 duringthe overall operation of the protective device shown in FIG. 1.

In the operation of the instantaneous tripping circuit 300, the base ofthe transistor Q18 is held at the regulated unidirectional potential atthe positive conductor P2. The voltage at the emitter of the transistorQ18 varies with-and is directly proportional to the highestunidirectional voltage across the resistors R1, R2 and R3 and, in turn,to the highest instantaneous line current flowing in the conductors L1,L2 and L3. More specifically, the voltage at the emitter of thetransistor Q18 is equal to the voltage at the positive conductor P3 plusthe voltage drop across the resistor R89 which depends, in part, on thesetting of the rheostat R42. As long as the highest instantaneous linecurrent flowing in the conductors L1, L2 and L3 remains belowsubstantially a predetermined or threshold value, the emitter-basecircuit of the transistor Q18 is reverse biased and the transistor Q18is substantially nonconducting or cutoff. As long as the transistor 018is substantially nonconducting or cutoff, the current flow through theresistor R25 in the collector circuit of the transistor Q18 issubstantially negligible and the potential at the anode of the diode D40is relatively close to the potential at the common or negative conductorN1 with the diode D40 being normally reverse biased or blocked due tothe potential which is applied to the cathode of the diode D40 from thepositive conductor P3 through the diode D45, the resistor R and thediode D46. When the highest instantaneous line current flowing in one ofthe conductors L1, L2 and L3 exceeds substantially the predetermined orthreshold value to which the instantaneous tripping circuit 300 isadjusted to respond and the corresponding highest instantaneousunidirectional voltage across the resistors R1, R2 and R3 exceedssubstantially a predetermined value, the voltage at the emitter of thetransistor Q18 increases in a positive direction sufficiently to forwardbias the emitter-base circuit of the transistor Q18 and to actuate thetransistor Q18 to substantially a saturated condition. Due to theincreased current flow in the emitter-collector path of the transistorQ18, the voltage drop across the resistor R25 increases to forward biasthe diode D and the output current of the instantaneous tripping circuit300 from the collector of the transistor Q18 flows through the diode D40and into the emitter-base circuit of the transistor Q15 to actuate theoutput level detecting circuit 410 to, in turn, actuate the siliconcontrolled rectifier 017 to a substantially congizatiori of the tripcoil in a substantially instantaneous manner without any intentionaltime delay. In the operation of the instantaneous tripping circuit 300,it is to be noted that as the highest instantaneous line current in theconductors L1, L2 and L3 increases toward the predetermined value towhich the instantaneous tripping circuit 300 responds, the control means270 which forms part of the level detecting means 260 of the long timedelay tripping circuit 200 will be actuated from a normallysubstantially saturated condition to a substantially nonconducting orcutoff condition prior to the operation of the instantaneous trippingcircuit 300 to thereby eliminate the relatively low resistance path tothe common or negative conductor N1 from the emitter of the transistorQ15 which would otherwise divert the output current of the instantaneoustripping circuit 300 away from the emitter of the transistor Q15.

Referring to FIG. 4, the operation of the instantaneous tripping circuit300 is indicated by the curves 910, 912 and 916. The minimuminstantaneous overload current to which the instantaneous trippingcircuit 300 may be adjusted to respond by the setting of the rheostatR42 is indicated by the predetermined overload current, as indicated bythe vertical curve 912, and the highest instantaneous line currentflowing in the conductors L1, L2 and L3 exceeds the instantaneouspredetermined current to which the instantaneous tripping circuit 300 isadjusted, as indicated by curve 912, the tripping time decreasesslightly along the lower portion of the curve 916 for values in excessof the maximum instantaneous current indicated by the curve 912. Thereason for this is that the curves shown are those for a trip operationfrom a no-load condition. In other words, for the purpose of thesecurves, it is assumed that no current is flowing in the conductors L1,L2 and L3 prior to the occurrence of the overcurrent condition. Thedelay in instantaneous tripping is due to the time taken to charge thecapacitor C13 to a level which is sufficient to operate the tripsolenoid 36. The circuit means 150, previously described, inhibits anytripping operation until the capacitor C13 has sufficient charge tooperate the trip coil 36. It is to be noted that the setting of theinstantaneous tripping circuit 300 determines the upper end of the rangeof overload currents to which the long time delay tripping circuit 200responds, since when the highest instantaneous line current flowing inthe conductors L1, L2 and L3 exceeds the predetermined current to whichthe instantaneous tripping circuit 300 responds, the trip coil 36 of thecircuit breaker CB will be energized substantially instantaneously asdetermined by the operating characteristics of the instantaneoustripping circuit 300, as indicated graphically in FIG. 4, without anyintentional time delay being introduced prior to the energization of thetrip coil 36. It is also important to note that the energization of thetrip coil 36 in response to both the long time delay tripping circuit200 and the instantaneous tripping circuit 300 occurs independentlyeither after a predetermined time delay which varies substantiallyinversely in the case of the long time delay tripping circuit 200 orsubstantially instantaneously in response to the operation of theinstantaneous tripping circuit 300. The operation of the instantaneoustripping circuit 300 may be inhibited or prevented in response to theclosing of the main contacts BCl, BC2 and BC3 by the use of an auxiliarycontact whose operation is coordinated with those of the main contactsof the circuit breaker CB and which is connected to the terminal 144 ofthe power supply input circuit 100 of the protective device shown inFIG. 1 and which, as shown in FIG.

copending application Ser. No. 765,552 filed by W. H. South and J H.Taylor which is assigned to the same assignee as the presentapplication.

SHORT DELAY TRIPPING CIRCUIT 500 Referring now to the short delaytripping circuit 500 which is indicated in FIG. 1 and shown in detail inFIG. 3, the short delay tripping circuit 500 is connected between thefirst auctioneering circuit and to the output circuit 400 to respond tothe highest instantaneous line current flowing in the conductors L1, L2and L3, when the instantaneous highest line current exceedssubstantially a predetermined or threshold value to actuate the outputcircuit 400 to energize the trip coil 36 following a substantially fixedor predetermined time delay which remains at the same predetermined'value independently of the magnitude of the highest instantaneouscurrent in excess of the predetermined value. It is to be noted that theshort delay tripping circuit 500 may be employed, where required, incombination with the long time delay tripping circuit 200 and theinstantaneous tripping circuit 300 and that the short delay trippingcircuit 500 independently actuates the output circuit 400 to energizethe trip coil 36 with the predetermined current to which the short delaytripping circuit 500 responds being coordinated with the range ofoverload currents to which the long time delay tripping circuit 200responds and the predetermined instantaneous current to which theinstantaneous tripping circuit 300 responds.

More specifically, the short delay tripping circuit 500 comprises thePNP transistors Q1 1 and Q12 and a voltage dividing network whichincludes the resistors R19 and R20 and the rheostat R40 which areconnected in series with one another between the variable voltage outputconductor V1 of the first auctioneering circuit 110 and the positiveconductor P3. The base of the transistor Q11 is connected to thejunction point between the resistors R19 and R20, while the emitter ofthe transistor Q11 is directly connected to the positive conductor P1.The diode D36 is connected between the base and the emitter of thetransistor Q11 to protect the emitter-base circuit of the transistor Q11from excessive reverse bias by limiting the maximum reverse voltageapplied to the emitter-base circuit of the transistor Q1 1 to theforward voltage drop of the diode D36. The input voltage of the shortdelay tripping circuit 500 which is in the sum of the voltage dropsacross the rheostat R40 and resistor R19 is substantially equal to thehighest unidirectional voltage across the resistors R1, R2 and R3 and,in turn, is directly proportional to the highest instantaneous linecurrent flowing in the conductors L1, L2 and L3. The forward voltagedrop in the emitter-base circuit of the transistor Q1 1 compensates theinput voltage of the short delay tripping circuit 500 for the forwardvoltage drop across one of the diodes D17, D18 and D19 of the firstauctioneering circuit 1 10. The collector of the transistor Q1 1 isdirectly connected to the base of the transistor Q12 and also to thecommon or negative conductor N1 through the collector load resistor R21.The emitter of the transistor Q12 is also directly connected to thepositive conductor P1, while the collector of the transistor Q12 isconnected to the common or negative conductor N1 through the collectorload resistor R22 and through the diode D38 to the upper side of thetimingor integrating capacitor C7 of the short delay tripping circuit500. In order to delay the reset of the short delay tripping circuitfollowing the end of a period of time during which the highestinstantaneous line current flowing in the line conductors L1, L2 and L3exceeds the predetermined value to which the short delay trippingcircuit 500 is adjusted to respond by the setting of the rheostat R40,the capacitor C6 is connected between the emitter and the collector ofthe transistor Q12 between the positive conductor P1 and the upper endof the resistor R22. In order to provide a substantially fixed orpredetermined time delay between the start of an instantaneousovercurrent which exceeds the predetermined value and to which the shortdelay tripping circuit 500 is adjusted to respond, an R-C timing circuitis provided as part of the short delay tripping circuit 500 whichincludes the rheostat R41, the resistor R23 and the timing capacitor C7,with the rheostat R41 and the resistor R23 being connected in serieswith one another between the positive conductor P1 and the upper side ofthe timing capacitor C7. The upper side of the timing capacitor C7 isalso connected to the emitter of the transistor Q15 which forms part ofthe output level detecting circuit 410 of the output circuit 400 throughthe normally reverse biased or blocked diode D37.

The lower side of the timing capacitor C7 of the short delay trippingcircuit 500 is connected by the conductor 286 to the output of theauxiliary pulse generating circuit 240 at the collector of thetransistor Q3 which forms part of the auxiliary pulse generating circuit240 in order that the lower side of the capacitor C7 be periodicallyraised in voltage with respect to the common or negative conductor N1 tothereby periodically increase the effective voltage at the upper side ofthe capacitor C7.

in the operation of the short delay tripping circuit 500, it is to benoted that the voltage dividing network which includes the rheostat R40and the resistor R19 and R20 along with the transistors Q11 and Q12comprises a level detecting circuit 510 having a time delay resetoperation of the general type which is disclosed in greater detail in acopending application Ser. No. 765,582 filed concurrently herewith by J.D. Watson and which is assigned to the same assignee as the presentapplication. As long as the highest instantaneous line current flowingin the conductors L1, L2 and L3 remains below sub stantially apredetermined or threshold value and the corresponding highestinstantaneous unidirectional voltage across the resistors R1, R2 and R3remains below the corresponding predetermined or threshold value, thetransistor Q11 will be in a normally saturated condition since theemitter base circuit of the transistor Q11 will be forward biased withthe voltage at the conductor P1 being greater than the voltage at thebase of the transistor Q11. The predetermined highest instantaneouscurrent to which the short delay tripping circuit is adjusted to respondis determined by the setting of the rheostat R40. As long as the highestinstantaneous current flowing in the conductors L1, L2 and L3 remainbelow the predetermined current to which the short delay trippingcircuit 500 is set to respond by the adjustment of the rheostat R40, thetransistor Q11 will be carrying saturated current in theemitter-collector path with the voltage at the base of the transistorQ12 with respect to the common conductor N1 being determined by thevoltage drop across the resistor R21 due to the collector current of thetransistor 011. When the transistor Q11 is carrying saturated current,the emitter-base circuit of the transistor Q12 will be biased atsubstantially zero voltage and the transistor Q12 will be in asubstantially nonconducting or cutoff condition. As long as thetransistor Q12 is in a substantially cutoff or nonconducting condition,the voltage drop across the resistor R22 due to the emitter-collectorcurrent of the transistor Q12 will be substantially negligible and thevoltage at the cathode of the diode D38 will be relatively close to thatat the common or negative conductor with the diode D38 being forwardbiased to prevent the timing capacitor C7 from accumulating a chargefrom the positive conductor P1 through the rheostat R41 and the resistorR23.

Since the cathode of the diode D37 is normally maintained at a positivevoltage with respect to the common or negative conductor N1 through thediode D45 the re'sistorR35 and the diode 46 from the voltage at thepositive conductor P3, the diode D37 will normally be reversed biased orblocked since the voltage at the anode of the diode D37 will be equal tothe sum of the forward voltage drop of the diode D38 and the substantially negligible voltage drop across the resistor R22, as long asthe highest instantaneous line current flowing in the 'conductors L1, L2and L3 remains below the predetermined value to which the short delaytripping circuit 500 is adjusted to respond by the setting of therheostat R40. It is to be noted that as long as the transistor Q12 is ina normally substantially nonconducting or cutoff condition, thecapacitor C6 which is connected between the emitter and the collector ofthe transistor Q12 will be charged up to a voltage which is equal to thedifference in voltage between the conductors P1 and'Nl less asubstantially negligible voltage drop across the resistor R22.

When the highest instantaneous current flowing in the line conductorsL1, L2 and L3 exceeds substantially a predetermined or threshold valueto which the short delay tripping circuit 500 is adjusted to respond bythe setting of the rheostat R40, the current which flows in the voltagedividing network which includes the rheostat R40 and the resistor R19and theresistor R20 will increase until the voltage at the base of thetransistor Q11 increases in a positive direction to reverse bias theemitter-base circuit of the transistor Q6 which will then be actuated toa substantially nonconducting or cutoff condition. When the transistorQ11 is actuated to a substantially cutoff or nonconducting condition,the current in the emitter-collector path of the transistor Q11 willdecrease to a negligible value and the current which flows in theresistor R21 will now flow from the positive conductor Pl through theemitter-base circuit of the transistor Q12. The transistor Q12 will thenbe actuated to a substantially saturated condition. When the transistorQ12 is actuated to a substantially saturated condition, the current inthe emitter-collector path of the transistor Q12 will increase tothereby cause an increased voltage drop across the resistor R22 whichwill then reverse bias or block the diode D38 to permit the timingcapacitor CT to start charging from the positive conductor P1 throughthe rheostat R41 and the resistor R23. Assuming that the overcurrentcondition to which the short delay tripping circuit 500 is adjusted torespond continues for substantially a predetermined or fixed time delaywhich is determined by the setting of the rheostat R41, the resistor R23and the capacitor C7 along with the regulated voltage at the conductorP1, the voltage at the upper side of the timing capacitor C7 which isperiodically "increased by the auxiliary voltage pulses from theauxiliary pulse generating circuit 240 which forms part of the long timedelay tripping circuit 200, will be sufficient to forward bias the diodeD37. When the diode D37 is forward biased, current will flow from theconductor P1 through the rheostat R41 and the resistor R23 to cause abase drive current to flow through the diode D37 into the emitter-basecircuit of the transistor Q15 of the output level detecting circuit 410to actuate the silicon controlled rectifier Q17 to a substantiallyconducting condition to thereby energize the trip coil 36 of the circuitbreaker CB and actuate the circuit breaker CB to an open condition.

It is to be noted that when the transistor Q12 is actuated to asubstantially saturated conditionin response to the highestinstantaneous current which flows in the line conductors L1, L2 and L3,the capacitor C6 will rapidly discharge through the emitter-collectorpath of the transistor Q12. If the highest instantaneous current flowingin the conductors L1, L2 and L3 exceeds the predetermined value to whichthe short delay tripping circuit 500 is adjusted to respond by thesetting of the rheostat R40 and then decreases below the predeterminedvalue, the transistor 011 will substantially instantaneously be returnedto a substantially saturated condition and the transistor Q12 willsubstantially instantaneously be restored to a substantially cutoff ornonconducting condition. The capacitor C6 will then start to charge fromthe conductors P1 and N1 through the resistor R22. While the capacitorC6 is charging, the voltage across the resistor R22 will graduallydecrease until the diode D38 is again forward biased to thereby rapidlydischarge the timing capacitor C7, if the overall time delay provided bythe short delay tripping circuit 500 has not been completed. In otherwords, after the operationof the short delay tripping circuit 500 hasbeen actuated by the instantaneous highest current flowing in theconductors L1, L2 and L3 and then the highest instantaneous currentdecreases below the predetermined value necessary to actuate the shortdelay tripping circuit 500 for a predetermined time period which isdetermined by the values of the capacitor C6 and the resistor R22 andthe voltage at the conductor Pl, the resetting of the short delaytripping circuit 500 will be delayed for a predetermined time intervalwhich may be slightly longer than one-half cycle of the alternatingcurrent flowing in the conductors L1,

L2 and L3 similarly to the level detecting circuit 260 of the long timedelay tripping circuit 200, as previously described. On the other handif the highest instantaneous current flowing in the line conductors L1,L2 and L3 exceeds the substantially predetermined or threshold value towhich the short delay tripping circuit 500 is adjusted to respond by thesetting of the rheostat R40 and then decreases for a period of time lessthan the time delay provided in the reset of the short delay trippingcircuit 500, the timing out or accumulation of charge on the timingcapacitor C7 will continue in an uninterrupted fashion. It is to benoted that the substantially predetermined or fixed time delay providedin the overall operation of the short delay tripping circuit isindependent of the magnitude of the highest instantaneous line currentin the conductors L1, L2 and L3 for values of current in excess of thepredetermined value to which the short delay tripping circuit 500 isadjusted to respond by the rheostat R40 and may be adjusted or varied bythe setting of the rheostat R41.

Referring to FIG. 4, the minimum instantaneous overcurrent to which theshort delay tripping circuit 500 may be adjusted to respond is indicatedby the curve 850, while the maximum instantaneous overcurrent to whichthe short delay tripping circuit 500 may be adjusted to respond by thesetting of the rheostat R40 is indicated by the curve 852. On the otherhand, the minimum predetermined or fixed time delay for which the shortdelay tripping circuit 500 may be adjusted is indicated by the curve864, while the maximum substantially predetermined or fixed time delayfor which the short delay tripping circuit 500 may be adjusted by thesetting of the rheostat R41 is indicated by the curve 862. Whereprovided, the short delay tripping circuit 500 determines by thepredetermined instantaneous overcurrent to which it is adjusted torespond the upper limit of the range of overcurrent to which the longtime delay tripping circuit 200 will respond in a particularapplication, since if the highest instantaneous line current flowing inthe line conductors L1, L2 and L3 exceeds the predetermined value towhich the short delay tripping circuit is adjusted to respond by thesetting of the rheostat R40, the output circuit 400 will be actuated toenergize the trip coil 36 after substantially a predetermined or fixedtime delay independent of the value of the highest instantaneousovercurrent in excess of the instantaneous overcurrent to which theshort delay tripping circuit 500 is adjusted to respond. It is to benoted that the reset of the short delay tripping circuit 500 isaccomplished by the discharge of the capacitor C7 through the diode D38and the resistor R22 to the common or negative conductor N1, rather thanemploying a control means of the emitter follower type such as thecontrol means 270 which is provided as part of the level detectingcircuit 260 of the long time delay tripping circuit 200 as previouslydescribed since the timing capacitor C7 is normally of a lower valuethan the timing capacitor C4 which forms part of the long time delaytripping circuit 200. In summary, it is important to note that the shortdelay tripping circuit 500 where provided is arranged to independentlyactuate the output circuit 400 along with the long time delay trippingcircuit 200 and the instantaneous tripping circuit 300 where provided.

GROUND CURRENT TRIPPING CIRCUIT 600 Referring now to the ground currenttripping circuit 600 which is indicated in block form in FIG. 1 andwhich is shown in detail in FIG. 3, the ground current tripping circuit600 in general is connected between the ground current transformer T4and the output circuit 400 to actuate the output circuit 400 to energizethe trip coil 36 of the circuit breaker CB when the ground current assensed by the transformer T4 increases to substantially a predeterminedvalue or level. More specifically, the primary winding of the groundcurrent transformer T4 is connected between the neutral conductor NTl ofthe current transformers CT 1, GT2 and CT3 and the neutral conductor NT2 of the interposing transformers T1, T2 and T3. The terminal 42 at theupper end of the primary winding of the transformer T4 may be connectedto the ground conductor (not shown) of the electrical system whichincludes the conductors L1, L2 and L3 and which is to be provided withground current protection, where desired in a particular application.The output ground current from the transformer T4 which is available atthe conductors G12 and G13 is applied at the input terminals 612 and614, respectively, of a full wave bridge type rectifier which includesthe diodes D1, D2, D3 and D4 to obtain a unidirectional current outputwhich is directly proportional or varies in a substantial manner withthe ground current in the electrical system being protected. Thepositive output terminal of the full wave bridge rectifier whichincludes the diodes Dl through D4 is connected to the positive conductorP1 through the resistor R28 to develop a unidirectional voltage acrossthe resistor R28 which is directly proportional to or varies in asubstantially linear manner with the ground current in the electricalsystem being protected. The negative output terminal of the full wavebridge type rectifier which ineludes the diodes D1 through D4 isconnected to the common or negative conductor N1.

More specifically, the ground current tripping circuit 600 includes alevel detecting circuit 610 and a time delay circuit 620 which providesa substantially predetermined or fixed time delay between the time theground current exceeds substantially a predetermined value and the timethat the trip coil 36 is energized through the output circuit 400. Thelevel detecting circuit 610 of the ground current tripping circuit 600is similar to the leveldetecting circuit 510 of the short delay trippingcircuit, as just described. In particular, the input of the leveldetecting circuit 610 comprises the voltage dividing

1. An overcurrent protective device comprising first means adapted to beconnected to an alternating current circuit for deriving therefrom aunidirectional voltage which varies in a substantially linear mannerwith the current in the circuit, second means connected to said fIrstmeans for converting said unidirectional voltage to substantially apredetermined output current which varies in a substantially linearmanner with said unidirectional voltage, third means connected to saidsecond means for producing periodic output pulses of current having anaverage value which varies with substantially the square of said currentin the circuit, said third means including a capacitor connected to saidsecond means, means connected to said second means for charging saidcapacitor, a breakover device connected to said capacitor toperiodically break over and discharge said capacitor when the charge onsaid capacitor periodically increases from substantially a firstpredetermined level to substantially a second predetermined level, and aresistor connected to one side of said capacitor to delay the return ofthe charge on said capacitor to said first predetermined level tothereby assist in maintaining each of the output pulses of said thirdmeans at substantially a predetermined width, an additional capacitorconnected to said third means for accumulating a charge, fourth meansconnected to said first means to be responsive to the current in saidcircuit and connected to said additional capacitor for actuating saidadditional capacitor to be charged by said output pulses of current whensaid current in the circuit exceeds substantially a predetermined value,and fifth means connected to said additional capacitor for providing anoutput when the charge on said additional capacitor reachessubstantially a predetermined level.
 2. The combination as claimed inclaim 1 wherein said means for charging said capacitor of said thirdmeans comprises means for converting said unidirectional voltage of saidfirst means to an additional substantially predetermined output currentwhich varies in a substantially linear manner with said unidirectionalvoltage and which is applied to said capacitor, the frequency andmagnitude of said output pulses of current of said third means bothvarying in a substantially linear manner with said current in thecircuit.
 3. The combination as claimed in claim 1 wherein an additionalmeans is connected to said first means and to said fifth means foractuating said fifth means to provide an output substantiallyinstantaneously when the current in the alternating current circuitexceeds substantially a predetermined value which is relatively largerthan the predetermined value to which said fourth means responds toactuate said additional capacitor to be charged by said pulses ofcurrent.
 4. A polyphase overcurrent protective device for use with athree-phase alternating current circuit comprising first means forderiving from said circuit a unidirectional voltage which varies in asubstantially linear manner with the highest of the three phase currentsin said circuit, second means connected to said first means forconverting said unidirectional voltage to substantially a predeterminedoutput current which varies in a substantially linear manner with saidunidirectional voltage, third means connected to said second means forproducing periodic output pulses of current having an average valuewhich varies with substantially the square of the highest current in thecircuit, said third means including a capacitor connected to said secondmeans, means connected to said capacitor for charging said capacitor, abreakover device connected to said capacitor to periodically break overand discharge said capacitor when the charge on said capacitorperiodically increases from substantially a first predetermined level tosubstantially a second predetermined level, and a resistor connected toone side of said capacitor to delay the return of the charge on saidcapacitor to said first predetermined value to thereby assist inmaintaining each of the output pulses of said third means atsubstantially a predetermined width, an additional capacitor connectedto said third means for accumulating a charge, fourth means connected tosaid first means to bE responsive to the current in said circuit andconnected to said additional capacitor for actuating said additionalcapacitor to be charged by said output pulses of current when thehighest current in said circuit exceeds substantially a predeterminedvalue, and fifth means connected to said additional capacitor forproviding an output when the charge on said additional capacitor reachessubstantially a predetermined level.
 5. The combination as claimed inclaim 4 wherein said means for charging said capacitor of said thirdmeans comprises means for converting said unidirectional voltage of saidfirst means to an additional substantially predetermined output currentwhich varies in a substantially linear manner with said unidirectionalvoltage and which is applied to said capacitor, the frequency andmagnitude of said output pulses of current of said third means bothvarying in a substantially linear manner with said current in thecircuit.
 6. The combination as claimed in claim 4 wherein an additionalmeans is connected to said first means and to said fifth means foractuating said fifth means to provide an output substantiallyinstantaneously when the highest current in the alternating currentcircuit exceeds substantially a predetermined value which is relativelylarger than the predetermined value to which said fourth means respondsto actuate said additional capacitor to be charged by said pulses ofcurrent.
 7. A circuit breaker comprising three sets of separablecontacts, operating means for opening said sets of contacts, a pluralityof line conductors connected to said sets of contacts, a plurality ofcurrent transformers disposed to obtain three output currents which aresubstantially proportional to the currents in said conductors, and anovercurrent protective device disposed to be responsive to said outputcurrents and operatively connected to said operating means for producingan output to actuate said operating means to open said contacts, saidprotective device including first means connected to said currenttransformers for deriving a unidirectional voltage which varies in asubstantially linear manner with the highest of said output currents,second means connected to said first means for converting saidunidirectional voltage to substantially a predetermined output currentwhich varies in a substantially linear manner with said unidirectionalvoltage, third means connected to said second means for producingperiodic output pulses of current having an average value which varieswith substantially the square of the highest output current from saidcurrent transformers, said third means including a capacitor connectedto said second means, means connected to said capacitor for chargingsaid capacitor, a breakover means connected to said capacitor toperiodically break over and discharge said capacitor when the charge onsaid capacitor periodically increases from substantially a firstpredetermined level to substantially a second predetermined level, and aresistor connected to one side of said capacitor to delay the return ofthe charge on said capacitor to said first predetermined level tothereby assist in maintaining each of the output pulses of said thirdmeans at substantially a predetermined width, an additional capacitorconnected to said third means for accumulating a charge, fourth meansconnected to said first means to be responsive to the current in saidcircuit and connected to said additional capacitor to be charged by saidoutput pulses of current when said highest output current exceeds apredetermined value, and fifth means operatively connected between saidadditional capacitor and said operating means for producing an outputwhen the charge on said additional capacitor exceeds a predeterminedlevel to actuate said operating means to open said contacts.
 8. Thecombination as claimed in claim 7 wherein said means for charging saidcapacitor of said third means comprises means for converting saidunidirectional voltage of said first Means to an additionalsubstantially predetermined output current which varies in asubstantially linear manner with said unidirectional voltage and whichis applied to said capacitor, the frequency and magnitude of said outputpulses of current of said third means both varying in a substantiallylinear manner with said current in the circuit.
 9. The combination asclaimed in claim 7 wherein an additional means is connected to saidfirst means and to said fifth means for actuating said fifth means toprovide an output substantially instantaneously when the highest currentin the alternating current circuit exceeds substantially a predeterminedvalue which is relatively larger than the predetermined value to whichsaid fourth means responds to actuate said additional capacitor to becharged by said pulses of current.